目前晶片設計領域中正在推行、研究的包括：系統設計面有 SOC design methodology flow；測試方面有正在推行的 SOC Testing methodology；而在錯誤 模擬方面，最主要的課題是如何建立行為層次(Behavior level)中可用的錯誤模組 (Fault Model)。因為如果建立的錯誤模組(Fault model)無法有效對應到 RTL Fault Model 更甚至於 Gate Level Fault Model 的話，其錯誤模組可靠度就不足。當錯誤 模組的可靠度夠高時，則在行為、功能層次的錯誤模擬才有意義，建立在這之上 錯誤模擬的實驗結果才有可信度。
而如何在行為、功能層次上建立錯誤模組，其最主要的困難是與硬體程式撰 寫風格(HDL Coding Style)有極大的相依性(Dependence)，因為撰寫硬體時，並沒 有像在邏輯閘層次(Gate Level)那樣清楚的範圍定義；在行為層次單單宣告一組訊 號，其使用範圍有可能是控制訊號、資料傳輸線、暫存器…等，而使用方式則更 是多變化，完全是依據程式撰寫者的撰寫風格而有所變動。所以錯誤模組化時，
除了要得知使用者宣告的訊號之外，還要分析整個硬體程式碼內部的流程、架 構，以便建立適合於這組程式碼的錯誤模組，而如何在行為層次找出適當、足夠、
有效率的測試樣本，將是更複雜的課題。行為層次錯誤模擬的研究範圍，硬體語 言分析、錯誤模組化、測試樣本建立、錯誤模擬、錯誤分析等都是新興的挑戰，
如何建立完整、可信任、高效率的行為層次錯誤模擬環境將是一個高難度的挑戰。
參考文獻
[1] Barry W. Johnson, “Design and Analysis of Fault Tolerant Digital Systems”, Addison Wesley, 1989.
[2] D. Patterson, J.Hennessy, “Computer Organization & Design: The Hardware/Software Interface”, Morgan Kaufmann, 1998.
[3] J. Henessy, D. Patterson, “Computer Architecture A Quantitative Approach”, Morgann Kaufman, 1996.
[4] D. P. Siewiorek, “Reliable Computer System Design and Evaluation”, Digital Press, 1998.
[5] Harold J. Larson, “Introduction to Probability”, Addison Wesley, 1994.
[6] Eric Jenn, Jean Arlat, Marcus Rimen, Joakim Ohlsson and Johan Karlsson,
“Fault Injection into VHDL Models: The MEFISTO Tool”, FTCS-24, IEEE, pp.
66-75, 1994.
[7] H. R. Zarandi, S. G. Miremadi and A. Ejlali, “Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models,” 18th
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.
485-492, Nov. 2003.
[8] J. Gracia, J. C. Baraza, D. Gil, P. J. Gil, “Comparison and Application of Different VHDL-Based Fault Injection Techniques,” 16th
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 233-241,
October 2001.[9] D. Gil, R. Martinez, J. V. Musquets, J. C. Baraza and P.J. Gil, “Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System”, Dependable Computing - EDCC-3, pp. 191-208, 1999.
[10] H. Maderia, M. Rela, F. Moreira and J. G. Silva, “RIFLE: A General Purpose Pin-Level Fault Injector”, Dependable Computing - EDCC-1, pp. 199-216, 1994.
[11] J. Karlsson, P. Liden, P. Dahlgren, R. Johansson and U. Gunneflo, “Using Heavy-Ion Radiation to Validate Fault-Handling Mechanisms,” IEEE Micro, 14(1), pp. 8-23, Feb. 1994.
[12] G. A. Kanawati, N. A. Kanawati and J. A. Abraham, “FERRARI: A Tool for the Validation of System Dependability Properties”, FTCS-22, IEEE, pp.
336-344, July 1992.
[13] T. Delong, B. Johnson, Profeta III, “A Fault Injection Technique for VHDL Behavioral-Level Models”, IEEE Design and Test of Computers, Vol. 13, winter 1996.
[14] Peter Folkesson, Sven Svensson, Johan Karlsson, “A Comparison of Simulation Based and Scan Chain Implemented Fault Injection”, FTCS-28, IEEE, pp. 284-293, 1998.
[15] T. K. Tsai, M. C. Hsueh, H. Zhao, Z. Kalbarczyk and R. K. Iyer, “Stress-Based and Path-Based Fault Injection”, IEEE Trans. On Computers, Vol. 48, No. 11, pp. 1183-1201, Nov. 1999.
[16] D. Gil, J. C. Baraza, J. V. Musquets, and P.J. Gil, “Fault Injection into VHDL Models: Analysis of the Error Syndrome of a Microcomputer System”, Proc.
Of the 24th Euromicro Conference, Vol. 1, pp. 418-425, 1998.
[17] J. Ohlsson, M. Rimen and U. Gunneflo, “A Study of the Effects of Transient Fault Injection into a 32-bit RISC with Built-in Watchdog”, FTCS-22, pp.
316-325, July 1992.
[18] Yung-Yuan Chen, “Concurrent Detection of Processor Control Errors By Hybrid Signature Monitoring”, Dependable Computing - EDCC-3, pp. 437-454, 1999.
[19] M. Nicolaidis, “Efficient Implementation of Self-Checking Adders and ALUs,”
Proc. Twenty-third Fault-Tolerant Computing Symp., pp 586-595, June 1993.
[20] Jérome Boué, Philippe Pétillon, Yves Crouzet, “MEFISTO-L: A VHDL-Based Fault Injection Tool for the Experimental Assessment of Fault Tolerance”,
FTCS-28, IEEE, pp. 168-173, 1998.
[21] Kumar K. Goswami, Ravishankar K. Iyer, Luke Young, “DEPEND: A Simulation-Based Environment for System Level Dependability Analysis”,
IEEE Trans. On Computers, Vol. 46, No. 1, pp. 60-74, Jan. 1997.
[22] Cristian Constantinescu, “Validation of the Fault/Error Handling Mechanisms of the Teraflops Supercomputer”, FTCS-28, pp. 382-389, 1998.
[23] Cristian Constantinescu, “Teraflops supercomputer: architecture and validation of the fault tolerance mechanisms”, IEEE Trans. On Computers, Vol. 49, No. 9, pp. 886-894, Sep. 2000.
[24] Jeffrey A. Clark, Dhiraj K. Pradhan, “Fault injection: a method for validating computer-system dependability” IEEE Computer, Vol. 28, No. 6, pp.47-56, June 1995.
[25] Mei-Chen Hsueh; Tsai, T.K.; Iyer, R.K., “Fault injection techniques and tools”, IEEE Computer, Vol. 30, No. 4, pp. 75-82, April 1997.
[26] Synopsys, “VHDL Simulation Reference Manual”, Synopsys online document V1999.10.
[27] Model Technology, ModelSim SE/PLUS Reference manual version 5.7b, http://www.model.com, 2003.
[28] Yung-Yuan Chen, Shi-Jinn Horng and Hung-Chuan Lai, “An Integrated Fault-Tolerant Design Framework for VLIW Processors,” 18th
IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.
555-562, Nov. 2003.
[29] TMS320C6000 CPU and Instruction Set Reference Guide, Texas Instruments,