結論

本專題中，擁有閘極工程的 In0.45Al0.55As/InxGa1-xAs 線性漸變通道變晶式 HEMT 已成功研究且製造出來。擁有鎳金屬蕭基接觸之樣本 B 比起傳統閘極結 構的樣本 A 以有效地改善元件特性，這是由於降低離子撞擊現象。更進一步，

運用鎳金屬與表面鈍化層兩種技術使的樣本 C 與其他樣本比起來有較高的 GVS 值0.55V，較低輸出電導 2.1mS/mm，最佳線性 196mA/mm，電壓增益 174V/V，

崩潰電壓 24.7V，輸出功率 14.9dBm 與溫度穩定。因此，此 MHEMT 元件研究 藉由鎳金屬與矽氮化物表面鈍化層改善了離子撞擊與紐結效應使其在高增益應 用和高功率微波電路上能穩定操作。

最後，更進一步改善元件特性，以下是我們建議可能使用的方法：

1. 用其他金屬(例如鈦,鉑)來做擁有矽氮化物鈍化層的蕭積閘極可以增強元件的 特性。

2. 利用自動較準的 T-閘極或空氣橋技術以便於降低閘極阻值和修除邊牆效應。

3. 分析元件的一致性與可靠性。

參考資料

[1] M. Kao, P. M. Smith, P. Ho, P. Chao, K. H. G. Duh, A. A. Jabra, and J. M.

Ballingall, “Very high power-added efficiency and low-noise 0.15-μm gate length pseudomorphic HEMT’s,” IEEE Electron Device Lett., vol. 10, p. 580, 1989.

[2] G. M. Metze, J. F. Bass, T. T. Lee, A. B. cornfield, J. L. Singer, H. L. hung, H. C.

Huang, and K. P. Pande, “High-gain, V-band, low-noise MMIC amplifiers using pseudomorphic MODFETs,” IEEE Electron Device Lett., vol. 11, p. 24, 1990.

[3] A. Ketterson, J. W. Seo, M. Tong, K. Nummila, D. Ballegeer, S. M. Kang, K.y.

Cheng, and I. Adesida, “A 10-GHz bandwidth pseudomorphic GaAs/InGaAs/AlGaAs MODFET-based OEIC receiver,” IEEE Trans. Electron

Devices, vol 39, p. 2676, 1992.

[4] C. S. Wu, C. K. Pao, W. Yau, H. Kanber, M. Hu, S. X. Bar, A. Kurdoghlian, Z.

bardai, D. Bosch, C. Seashore, and M. Gawronski, “Pseudomprphic HEMT manufacturing technology for multifunctional Ka-band MMIC applications,”

IEEE Microwave Theory and Tech., vol. 43, p. 257, 1995.

[5] S. E. Rosenbaum, B. K. Kormanyos, L. M. Jellian, M. Matloubian, A. S. Brown, L. E. Larson, L. D. Nguyen, M. A. Thompson, L. P. B. Katehi, and G. M. Rebeiz,

“155- and 213-GHz AlInAs/GaInAs/InP HEMT MMIC oscillators,” IEEE

Microwave Theory and Tech., vol 43, p. 927, 1995.

[6] P. N. tung, P. Delescluse, D. Delagebeaudeuf, M. Laviorn, J. Chaplart, and N. T.

Linh, “High speed low power DCFL using planar two-dimensional electron gas FET technology,” Electron. Lett., vol. 18, p. 517, 1982.

[7] S. sen, M. K. Pandey, R. S. Gupta, “Two-dimensional C-V model of AlGaAs/GaAs modulation doped field effect transistor (MODFET) for high frequency applications,” IEEE Trans. Electron Devices, vol. 46, p. 1818, 1999.

[8] F. Ali and A. Gupta, “HEMTs and HBTs; devices, fabrication, and circuits,”

Artech House, Boston London, 1991.

[9] M. T. Yang, Y. J. Chan, C. H. Chen, J. I. Chyi, R. M. Lin, and J. L. Shieh,

“Characteristics of pseudomorphic AlGaAs/InxGa1−xAs (0 ≤ x ≤ 0.25) doped-channel field-effect transistors.” J. Appl. Phys., vol. 76, pp. 2494, 1994.

[10] C. Nguyen and M. Micovic, “The state-of-the-art of GaAs and InP power devices and amplifiers.” IEEE Trans. Electron Devices, vol. 48, pp. 472, 2001.

[11] L. D. Nguyen, A. S. Brown, M. A. Thompson, and L. M. Jelloian, “50-nm self-aligned gate pseudomorphic AlInAs/GaInAs high electron mobility transistors,” IEEE Trans. Electron. Devices, vol. 39, no. 12, pp. 2007-2014, Dec.

1992.

[12] H. S. Yoon, J. H. Lee, J. Y. Shim, S. J. Kim, D. M. Kang, J. Y. Hong, W. J.

Chang, and K. H. Lee, “Low noise characteristics of double-doped In0.52Al0.48As–In0.53Ga0.47As power metamorphic HEMT on GaAs substrate with wide head T-shaped gate,” in Proc. Indium Phosphide and Related Materials, 2002, pp. 201-204.

[13] Behet, M., Van Der Zanden, K., Borghs, G., and Behres, A., “Metamorphic InGaAs/InAlAs quantum well structure grown on GaAs substrate for high electron mobility transistor applications,” Appl. Phys. Lett., 1998, vol. 73, p.

2760-2762.

[14] Contrata, W., Iwata, N., “Double-doped In^0.35Al^0.65As/In^0.35Ga^0.65 As power heterojunction FET on GaAs substrate with 1 W output power,” IEEE Electron

Device Letters, vol. 20, July 1999 p.369 – 371.

[15] Hoke, W.E., Lemonias, P.J., Lyman, P.S., Torabi, A., Marsh, P.F., Mctaggart, R.A., Lardizabal, S.M., and Hetzler, K., “Molecular beam epitaxial growth and device performance of metamorphic high electron mobility transistor structures fabricated on GaAs substrates,” J. Vac. Sci. Technol. B, 1999, vol. 17, p.1131-1135.

[16] K. Ouchi., T. Mishima, M. Kudo, and H. Ohta, “Gas-source molecular beam epitaxy growth of metamorphic InP/In0.5Al0.5As/In0.5Ga0.5As/InAsP high-electron-mobility structures on GaAs substrates,” Jpn. J. Appl. Phys., vol.

41, pp. 1004-1007, 2002.

[17] S. Bollaert, Y. Cordier, M. Zaknoune, H. Happy, V. Hoel, S. Lepilliet, D. Théron

and A. Cappy, “The indium content in metamorphic InxAl1−xAs/InxGa1−xAs HEMTs on GaAs substrate: a new structure parameter.” Solid-State

Electronics, Vol. 44, Issue 6, 2000, pp. 1021-1027.

[18] S. Bollaert, Y. Cordier, M. Zaknoune, H. Happy, S. Lepilliet, and A. Cappy,

“0.06 μm Gate length metamorphic In0.52Al0.48As/In0.53Ga0.47As HEMTs on GaAs with high fT and fmax,” in Proc. Indium Phosphide Rel. Mater., 2001, pp.

192-195.

[19] Suemitsu T., Enoki T., Sano N., Tomizawa M., Ishii Y., “An analysis of the kink phenomena in InAlAs/InGaAs HEMT's using two-dimensional device simulation,” Electron Devices, IEEE Transactions on, vol. 45, no. 12, Dec. 1998 p.2390-2399.

[20] Somerville M. H., Ernst A., del Alamo J. A., “A physical model for the kink effect in InAlAs/InGaAs HEMTs,” Electron Devices, IEEE Transactions on, vol.

47, no. 5, May 2000 p.922-930.

[21] Horio K., Wakabayashi A., “Numerical analysis of surface-state effects on kink phenomena of GaAs MESFETs,” Electron Devices, IEEE Transactions on, vol.

47, no. 12, Dec. 2000 p.2270-2276.

[22] Haruyama J., Negishi H., Nishimura Y., Nashimoto Y., “Substrate-related kink effects with a strong light-sensitivity in AlGaAs/InGaAs PHEMT,” Electron

Devices, IEEE Transactions on, vol. 44, no. 1, Jan. 1997 p.25-33.

[23] Fazal Ali and Alitya Gupta, “HEMTs and HBTs; Devices, Fabrication, and Circuits”, p.82.

[24] J. C. Huang, M. Zaitlin, W. Hoke, M. Adlerstein, P. Lyman, P. Saledas, G.

Jackson, E. Tong, and G. Flynn, “A high-gain, low-noise 1/2-μm pulse-doped pseudomorphic HEMT,” IEEE Electron Device Lett., vol. 10, p. 511, 1989.

[25] A. Fathimulls, J. Abrahams, T. Loughran, H. Hier, “High performance InAlAs/InGaAs HEMTs and MESFETs”, IEEE Electron Device Letters, vol. 28, no. 19, p.1849, 1992.

[26] S. R. Bahl, J. A. del Alamo, “Elimination of mesa sidewall gate leakage in

InAlAs/InGaAs HFETs”, Electron Devices, IEEE Transactions on, vol. 13, no.

4, p.195, 1992.

[27] S. R. Bahl, M. H. Leary, J. A. del Alamo, “Mesa sidewall gate leakage in InAlAs/InGaAs HFETs”, Electron Devices, IEEE Transactions on, vol. 39, no.

9, p.2037, 1992.

[28] G. I. Ng, W. P. Hong, D. Pavlidis, M. Tutt, P. K. Bhattacharya, “Characteristics of stained InGaAs/InAlAs HEMT with optimized transport parameters”, IEEE

Electron Device Letters, vol. 9, no. 9, p439, 1988.

[29] S. R. Bahl, B. R. Bennett, J. A. Alamo, “Doubly stained InAlAs/n-InGaAs HFET with high breakdown voltage”, IEEE Electron Device Letters, vol. 14, no.

1, p. 22, 1993.

[30] R. T. Hsu, H. M. Shieh, W. C. Hsu, and T. S. Wu, “Enhanced current driving capability GaAs/graded InxGa1-xAs high electron mobility transisitor,”

Solid-State Electron, vol. 36, p.1143, 1993.

[31] Y. J. Li, J. S. Su, Y. S. Lin and W. C. Hsu, “Investigation of a graded channel InGaAs/GaAs heterostructure transistor,” Superlattices and Microstructures, vol.

28, p.47, 2000.

[32] W. C. Hsu, C. L. Wu, M. S. Tsai, C. Y. Chang, W. C. Liu, H. M. Shieh,

“Characterization of high performance inverted delta modulation doped (IDMD) GaAs/InGaAs psedomophic heterostructure FETs”, IEEE Trans. on, Electron

Devices, vol. 9, no. 1, p.22, 1993.

[33] C. S. Lee, Y. J. Chen, W. C. Hsu, K. H. Su, J. C. Huang, D. H. Huang, and C. L.

Wu, “High-temperature threshold characteristics of a symmetrically graded InAlAs/InxGa1–xAs/GaAs metamorphic high electron mobility transistor.” Appl.

Phys. Lett., 88, 223506 (2006).

[34] W. C. Liu, W. L. Chang, W. S. Lour, S. Y. Cheng, Y. H. Shie, J. Y. Chen, W. C.

Wang, H. J. Pan, “Temperature-dependent investigation of a high-breakdown voltage and low-leakage current In0.49Ga0.51As/In0.15Ga0.85As pseudomorphic HEMT,” IEEE Electron Device Lett., vol. 20, p. 274,1998.

S.I GaAs Substrate

i-In

_x

Al

_1-x

As metamorphic buffer layer 3000Ǻ X=0→0.55

i-In

_x

Ga

_1-x

As linearly-graded channel layer 180Ǻ X=0.63→0.53

i-In

_0.45

Al

_0.55

As spacer layer 30Ǻ i-In

0.45

Al

0.55

As Schottky layer 250Ǻ n-In

_0.53

Ga

_0.47

As capping layer

250Ǻ

Gate dimension : 1.2×100μm ²

i-In

_0.45

Al

_0.55

As spacer layer 30Ǻ

δ doping

n

⁺

=1.0

×

10

¹²

cm

^-2

S.I GaAs Substrate

i-In

_x

Al

_1-x

As metamorphic buffer layer 3000Ǻ X=0→0.55

i-In

_0.45

Al

_0.55

As buffer layer 3000Ǻ

S.I GaAs Substrate

i-In

_x

Al

_1-x

As metamorphic buffer layer 3000Ǻ X=0→0.55

i-In

_x

Ga

_1-x

As linearly-graded channel layer 180Ǻ X=0.63→0.53

i-In

_0.45

Al

_0.55

As spacer layer 30Ǻ i-In

0.45

Al

0.55

As Schottky layer 250Ǻ n-In

_0.53

Ga

_0.47

As capping layer

250Ǻ

Gate dimension : 1.2×100μm ²

i-In

_0.45

Al

_0.55

As spacer layer 30Ǻ

δ doping

n

⁺

=1.0

×

10

¹²

cm

^-2

Figure 4-1 The cross section of the Sample A

S.I GaAs Substrate

i-In_xAl_1-xAs metamorphic buffer layer 3000Ǻ X=0→0.55

i-In_xGa_1-xAs linearly-graded channel layer 180Ǻ X=0.63→0.53

i-In_0.45Al_0.55As spacer layer 30Ǻ i-In_0.45Al_0.55As Schottky layer 250Ǻ n-In_0.53Ga_0.47As capping layer

250Ǻ

Gate dimension : 1.2×100μm²

i-In_0.45Al_0.55As spacer layer 30Ǻ

δ

doping n

⁺

=1.0 × 10

¹²

cm

^-2

S.I GaAs Substrate

i-In_xAl_1-xAs metamorphic buffer layer 3000Ǻ X=0→0.55

i-In_0.45Al_0.55As buffer layer 3000Ǻ

S.I GaAs Substrate

i-In_xAl_1-xAs metamorphic buffer layer 3000Ǻ X=0→0.55

i-In_xGa_1-xAs linearly-graded channel layer 180Ǻ X=0.63→0.53

i-In_0.45Al_0.55As spacer layer 30Ǻ i-In_0.45Al_0.55As Schottky layer 250Ǻ n-In_0.53Ga_0.47As capping layer

250Ǻ

Gate dimension : 1.2×100μm²

i-In_0.45Al_0.55As spacer layer 30Ǻ

δ

doping n

⁺

=1.0 × 10

¹²

cm

^-2

Figure 4-2 The cross section of the Sample B

S.I GaAs Substrate

i-In_xAl_1-xAs metamorphic buffer layer 3000Ǻ X=0→0.55 i-In_0.45Al_0.55As Schottky layer 250Ǻ

Gate dimension : 1.2×100μm²

i-In_xGa_1-xAs linearly-graded channel layer 180Ǻ X=0.63→0.53

S.I GaAs Substrate

i-In_xAl_1-xAs metamorphic buffer layer 3000Ǻ X=0→0.55

i-In_0.45Al_0.55As buffer layer 3000Ǻ

S.I GaAs Substrate

i-In_xAl_1-xAs metamorphic buffer layer 3000Ǻ X=0→0.55

i-In_0.45Al_0.55As buffer layer 3000Ǻ

S.I GaAs Substrate

i-In_xAl_1-xAs metamorphic buffer layer 3000Ǻ X=0→0.55 i-In_0.45Al_0.55As Schottky layer 250Ǻ

Gate dimension : 1.2×100μm²

i-In_xGa_1-xAs linearly-graded channel layer 180Ǻ X=0.63→0.53

Figure 4-3 The cross section of the Sample C

0 0.5 1 1.5 2 2.5

Drain-Souce voltage (V)

0 100 200 300 400 500 600

D ra in c ur re nt d ens it y (mA /mm)

V _GS =0.5 ~ -3V -0.5V/step

Figure 4-4 Current-Voltage characteristics of Sample A at 300K

0 0.5 1 1.5 2 2.5

Drain-Souce voltage (V)

0 100 200 300 400 500 600

D ra in c ur re nt d ens it y (mA /mm)

V _GS =0.5 ~ -2V -0.5V/step

Figure 4-5 Current-Voltage characteristics of Sample B at 300K

0 0.5 1 1.5 2 2.5

Drain-Souce voltage (V)

0 100 200 300 400 500

D ra in c ur re nt d ens it y (mA /mm)

V _GS =0.5 ~ -2V -0.5V/step

Figure 4-6 Current-Voltage characteristics of Sample C at 300K

0 0.5 1 1.5 2 2.5

Drain-Souce voltage (V)

0 200 400 600

D ra in c ur re nt d ens it y (mA /mm) V

_GS

=0.5 ~ -3V

-0.5V/step

Sample A Sample B Sample C

Figure 4-7 Current-Voltage characteristics of our studied InAlAs/InGaAs

metamorphic HEMTs at 300K

-2.5 -2 -1.5 -1 -0.5

Gate voltage (V)

-400 -300 -200 -100 0

G at e cu rren t d en si ty ( uA /mm)

V _DS =1 ~ 2.5V 0.5V/step

Figure 4-8 Gate current density versus gate voltage at different V

_DS

for Sample A at 300K

-2 -1.6 -1.2 -0.8 -0.4

Gate voltage (V)

-120 -80 -40 0

G at e cu rren t d en si ty ( uA /mm)

V

_DS

=1 ~ 2.5V 0.5V/step

Figure 4-9 Gate current density versus gate voltage at different V

_DS

for Sample B at 300K

-1.2 -0.8 -0.4 0

Gate voltage (V)

-20 -16 -12 -8 -4 0

G at e cu rren t d en si ty ( uA /m m )

V

_DS

=1 ~ 2.5V 0.5V/step

Figure 4-10 Gate current density versus gate voltage at different V

_DS

for Sample C at 300K

-2 -1 0 1

Gate voltage (V)

0 100 200 300 400 500

Ex tr in si c t ra ns co nd uct an ce ( m S/ mm)

0 100 200 300 400 500 600

Dra in cu rren t d en si ty ( m A /mm)

V

_DS

= 2V

Figure 4-11 Extrinsic transconductance and saturation drain current

density of Sample A of V

DS

=2V at 300K

-2 -1 0 1

Gate voltage (V)

0 100 200 300 400

Ex tr in si c t ra nsco nd uct an ce ( m S/ mm)

0 100 200 300 400 500

Dra in cu rren t de ns it y ( m A /mm)

V

_DS

= 2V

Figure 4-12 Extrinsic transconductance and saturation drain current

density of Sample B of V

DS

=2V at 300K

-1.5 -1 -0.5 0 0.5 1

Gate voltage (V)

0 100 200 300 400

Ex tr in si c t ra ns co nd uct an ce ( m S/ mm)

0 100 200 300 400 500

Dra in cu rren t d en si ty ( m A /mm)

V

_DS

= 2V

Figure 4-13 Extrinsic transconductance and saturation drain current

density of Sample C of V

DS

=2V at 300K

-2 -1 0 1

Gate voltage (V)

0 100 200 300 400 500

Ex tr in si c t ra ns co nd uct an ce ( m S/ mm)

0 100 200 300 400 500 600

Dra in cu rren t d en si ty ( m A /mm)

V

_DS

= 2V ^{Sample A}

Sample B Sample C

Figure 4-14 Extrinsic transconductance and saturation drain current

density of our studied InAlAs/InGaAs metamorphic

HEMTs at 300K

0 50 100 150 200 250 300 350 400 450 500 550

Drain current density (mA/mm)

0 100 200 300 400 500

E xt ri ns ic t ran sc on du ct an ce ( m S/ mm)

Sample A Sample B Sample C

V

_DS

= 2V

Figure 4-15 Extrinsic transconductance as a function of the drain current

density of our studied InAlAs/InGaAs metamorphic HEMTs

at 300K

-30 -25 -20 -15 -10 -5 0 5

Gate-Drain voltage (V)

-1 -0.5 0 0.5 1

G at e cu rren t d en si ty ( m A /mm)

Sample A Sample B Sample C

Figure 4-16 Breakdown voltage of our studied InAlAs/InGaAs

metamorphic HEMTs at 300K

0 0.5 1 1.5 2 2.5

Drain voltage (V)

0 100 200 300 400

Ex tr in si c t ra ns co nd uct an ce (m S/ m m ) an d o ut put c onduc ta nc e ( m S/m m )

0 2 4 6 8 10

V olt age g ain

V _GS = -1.5V

g _m

g _d A _v

Figure 4-17 The extrinsic transconductance, output conductance and

voltage gain characteristics versus drain voltage for Sample

A.

0 0.5 1 1.5 2 2.5

Drain voltage (V)

0 100 200 300 400

Ex tr in si c t ra ns co nd uct an ce (m S/ m m ) an d o ut put c onduc ta nc e ( m S/m m )

0 4 8 12

V olt age g ain

V _GS = -1V

g _m

g _d A _v

Figure 4-18 The extrinsic transconductance, output conductance and

voltage gain characteristics versus drain voltage for Sample

B.

0 0.5 1 1.5 2 2.5

Drain voltage (V)

0 100 200 300 400

Ex tr in si c t ra ns co nd uct an ce ( m S/ mm) an d o ut pu t co nd uct an ce ( m S/ m m )

0 40 80 120 160 200

V olt age gain

V _GS = -0.5V

g _d

g _m A _v

Figure 4-19 The extrinsic transconductance, output conductance and

voltage gain characteristics versus drain voltage for Sample

C.

0.1 1 10 100

Frequency (GH)

0 10 20 30 40 50

Gain ( dB )

f _t = 24.9 GHz

f _max = 64.3 GHz f _t f _max

V _DS = 2V V _GS = -1.65V

Figure 4-20 RF characteristics of Sample A at V

_DS

= 2V, V

_GS

= -1.65V for

gate dimension = 1.2×200 μm

²

0.1 1 10 100

Frequency (GH)

0 10 20 30 40 50

Gain ( dB )

f _t = 27.9 GHz

f _max = 70.1 GHz f _t

f _max

V _DS = 2V V _GS = -1.2V

Figure 4-21 RF characteristics of Sample B at V

_DS

= 2V, V

_GS

= -1.2V for

gate dimension = 1.2×200 μm

²

0.1 1 10 100

Frequency (GH)

0 10 20 30 40 50

Gain ( dB )

f _t = 21.5 GHz

f _max = 62.9 GHz f _t

f _max

V _DS = 2V V _GS = -0.5V

Figure 4-22 RF characteristics of Sample C at V

_DS

= 2V, V

_GS

= -0.5V for

gate dimension = 1.2×200 μm

²

-20 -10 0 10

Input power (dBm)

-10 -5 0 5 10 15 20 25

P ow er g ai n ( dB ) & out put po w er ( dB m )

0 4 8 12 16

Po w er a dd e ff ic ie nc y ( % )

P _out

Power gain

Power-Added efficiency

Figure 4-23 The output power, power gain and power added efficiency

(PAE) characteristics versus input power at 2.4 GHz for

Sample A.

-20 -10 0 10

Input power (dBm)

-10 -5 0 5 10 15 20 25

P ow er g ai n ( dB ) & out put po w er ( dB m )

0 10 20 30

Po w er a dd e ff ic ie nc y ( % )

P _out

Power gain

Power-Added efficiency

Figure 4-24 The output power, power gain and power added efficiency

(PAE) characteristics versus input power at 2.4 GHz for

Sample B.

-20 -10 0 10

Input power (dBm)

-10

P ow er g ai n ( dB ) & out put po w er ( dB m )

0

Po w er a dd e ff ic ie nc y ( % )

P _out

Power gain

Power-Added efficiency

Figure 4-25 The output power, power gain and power added efficiency

(PAE) characteristics versus input power at 2.4 GHz for

Sample C.

1 2 3 4 5 6 7 8 9 10

Frequency (GHz)

0 1 2 3 4 5

Noi se f ig ur e mi ni mum (dB )

4 8 12 16 20 24

As so ci at ed gai n ( dB )

frequency = 2.4GHz NFmin = 1.18dB

Associated Gain = 14.94dB

Figure 4-26 The minimum noise figure (NF

_min

) and the associated gain

characteristics versus frequency for Sample A.

1 2 3 4 5 6 7 8 9 10

Frequency (GHz)

0 1 2 3 4

Noi se f ig ur e mi ni mum (dB )

4 8 12 16 20 24

As so ci at ed gai n ( dB )

frequency = 2.4GHz NFmin = 0.90dB

Associated Gain = 16.62dB

Figure 4-27 The minimum noise figure (NF

_min

) and the associated gain

characteristics versus frequency for Sample B.

1 2 3 4 5 6 7 8 9 10

Frequency (GHz)

0 1 2 3 4 5 6

Noi se f ig ur e mi ni mum (dB )

4 8 12 16 20

As so ci at ed gai n ( dB )

freguency = 2.4GHz NFmin = 1.23dB

Associated Gain = 14.44dB

Figure 4-28 The minimum noise figure (NF

_min

) and the associated gain

characteristics versus frequency for Sample C.

-2 -1 0 1

Gate voltage (V)

0 100 200 300 400

Ex tr in si c t ra ns co nd uct an ce ( m S/ mm)

0 100 200 300 400 500 600

Dra in cu rren t d en si ty ( m A /mm)

300K 350K 400K 450K

V

_DS

=2V

Figure 4-29 Extrinsic transconductance and saturation drain current

density of Sample B from 300K to 450K.

-2 -1 0 1

Gate voltage (V)

0 100 200 300 400

Ex tr in si c Tra ns co nd uct an ce ( m S/ mm)

0 100 200 300 400 500

D ra in c ur re nt d ens it y ( m A /mm)

300K 350K 400K 450K

V

_DS

=2V

Figure 4-30 Extrinsic transconductance and saturation drain current

density of Sample C from 300K to 450K.

280 320 360 400 440 480

Temperature (K)

240 280 320 360 400 440

E xt ri ns ic t ran sc on du ct an ce ( m S/ mm)

Sample A Sample B Sample C

Figure 4-31 The relationships between the extrinsic transconductance and

temperature of our studied InAlAs/InGaAs metamorphic

HEMTs.

280 320 360 400 440 480

Temperature (K)

300 350 400 450 500 550

Ma xi m um d ra in cu rren t d en si ty ( m A /mm)

Sample A Sample B Sample C

Figure 4-32 The relationships between the maximum drain current

density and temperature of our studied InAlAs/InGaAs

metamorphic HEMTs.

280 320 360 400 440 480

Temperature (K)

-2.8 -2.4 -2 -1.6 -1.2 -0.8 -0.4

T hr es hol d vol tage ( V )

Sample A Sample B Sample C

Figure 4-33 The relationships between the threshold voltage and

temperature of our studied InAlAs/InGaAs metamorphic

HEMTs.

-6 -4 -2 0 2

Gate-Drain voltage (V)

-1 -0.5 0 0.5 1

G at e cu rren t d en si ty ( m A /mm)

300K 350K 400K 450K

Figure 4-34 Two-terminal gate-drain breakdown voltage characteristics of

Sample B from 300K to 450K.

-20 -15 -10 -5 0 5

Gate-Drain voltage (V)

-1 -0.5 0 0.5 1

G at e cu rren t d en si ty ( m A /mm)

300K 350K 400K 450K

Figure 4-35 Two-terminal gate-drain breakdown voltage characteristics of

Sample C from 300K to 450K.

在文檔中 運用閘極工程減緩砷化銦鋁/砷化銦鎵變晶式高電子移動率電晶體紐結效應之研製 (頁 27-65)