計畫產出論文

已發表之論文

[1] J.-C. Chan, N. T.-C. Chang, and T.-S.Chang,“ISID:In-order scan and indexed diffusion segmentation algorithm for Stereo Vision,” in Proc. of IEEE Int.

Symposium on Circuits and Systems, Seattle, U.S., 2008.

[2] T.-H. Tsai, N. Y.-C. Chang, and T.-S.Chang,“Datareuse analysis of local stereo matching,”in Proc. of IEEE Int. Symposium on Circuits and Systems, Seattle, U.S., 2008.

[3] L.-Y. Ku, S.-H. Wen, N. Y.-C. Chang, and T.-S.Chang,“A low-Cost real-time command control system based on stereo-vision and hand motion,”in Proc. of Conf. on Computer Vision, Graphics, and Image Processing, Taiwan, 2008.

[4] J.-C. Chan, N. Y.-C. Chang, Y.-C. Tseng, and T.-S. Chang, “Local belief aggregation for MRF-based color image segmentation,” in Proc. of Conf. on Computer Vision, Graphics, and Image Processing, Taiwan, 2008.

[5] Y.-C. Tseng, N. Y.-C. Chang, and T.-S.Chang,“Block-based belief propagation with in-placemessageupdating forstereo video,”in Proc. of IEEE Asia Pacific Conf. on Circuits and Systems, China, Macao, 2008.

[6] N. Y.-C. Chang, Y.-C. Tseng, and T.-S.Chang,“Analysisofcolorspaceand similarity measure impact on stereo block matching,” in Proc. of IEEE Asia Pacific Conf. on Circuits and Systems, China, Macao, 2008.

[7] Y.-C. Tseng, N. Y.-C. Chang, and T.-S. Chang, “Low-memory cost belief propagation architecture for disparity estimation,” in Proc. of IEEE Int.

Symposium on Circuits and Systems, Taipei, Taiwan, 2009.

[8] P.-H. Hsu, Y.-C. Tseng, and T.-S.Chang,“Low memory costbilateralfiltering using stripe-based sliding integralhistogram,”in Proc.ofIEEE Int’lSymposium on Circuits and Systems, Paris, France, 2010.

[9] Y.-R. Horng, Y.-C. Tseng, and T.-S.Chang,“Stereoscopicimagesgeneration with directionalGaussian filter,”in Proc.ofIEEE Int’lSymposium on Circuits and Systems, Paris, France, 2010.

[10] N. Y.-C. Chang, T.-H. Tsai, B.-H. Hsu, Y.-C. Chen, and T.-S. Chang,

“Algorithm and architectureofdisparity estimation with mini-census adaptive supportweight,”IEEE Trans. on Circuits and Systems for Video Technology, vol.

20, no. 6, pp. 792-805, June 2010,

[11] Y.-C. Tseng and T.-S. Chang, “Architecture design of belief propagation for real-timedisparity estimation,”IEEE Trans. on Circuits and Systems for Video Technology, vol. 20, no. 11, pp. 1555-1564, Nov. 2010.

[12] J. H. Tu and Lan-DaVan,“Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers,” IEEE Trans. Computers, vol. 58, no. 10, pp.

1346-1355, Oct. 2009. (SCI & EI, Full Paper)

[13] C. T. Lin, Y. C. Yu, and Lan-DaVan,“Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor,”IEEE Trans. VLSI Systs., vol. 16, no. 8, pp. 1058-1071, Aug. 2008. (SCI & EI, Full Paper)

[14] T. Y. Sheu, L. D. Van, T. R. Jung, C. W. Lin, and T. W. Chang, ”Low complexity subdivision algorithm to approximate Phong shading using forward difference,”inProc. IEEE Int. Symp. Circuits Syst. (ISCAS), May. 2009, pp.

2373-2376, Taipei, Taiwan.

[15] P. Y. Chen, L. D. Van, H. C. Reddy, and C. T. Lin, ”A new VLSI 2-D fourfold-rotational-symmetry filterarchitecturedesign,”inProc. IEEE Int. Symp.

Circuits Syst. (ISCAS), May. 2009, pp. 93-96, Taipei, Taiwan.

[16] I. H. Khoo, H. C. Reddy, L. D. Van, and C. T. Lin, ” 2-D digital filter architectureswithoutglobalbroadcastand somesymmetry applications,”inProc.

IEEE Int. Symp. Circuits Syst. (ISCAS), May. 2009, pp. 952-955, Taipei, Taiwan.

[17] L. Y. Lin, H. K. Lin, C. Y. Wang, L. D. Van, and J. Y.Jou, ”Hierarchical architecture for network-on-chip platform,” in Proc.VLSI-DAT, Apr. 2009, pp.

343-346, Hsinchu, Taiwan.

[18] P. Y. Chen, L. D. Van, H. C. Reddy, and C. T. Lin, ”A new VLSI 2-D diagonal-symmetry filter architecture design,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2008, pp. 320-323, Macao, China.

[19] T. R. Jung, L. D. Van, T. Y. Sheu, C. W. Lin, W. C. Fang, “Design of multi-modedepth buffercompression for3D graphicssystem,”inProc. IEEE Int. Conf. Multimedia and Expo. (ICME), July 2008, pp. 789-792, Hannover, Germany.

[20] T. R. Jung, L. D. Van, W. C. Fang, T. Y. Sheu, "Reconfigurable depth buffer compression design for 3D graphics system," in Proc. Int. Conf. MUE., Apr.

2008, pp. 470-474, Busan, Korea.

[21] Y.-C. Tseng, C.-H. Wu, Y.-W. Chen, T.-W. Wang, and W.-H. Peng, "On the Analysis and Design of Motion Sampling Structure for Advanced Motion-Compensated Prediction,"

IEEE Int’lConf.on ImageProcessing, 2010.

[22] T. W. Wang, Y. W. Chen, and W. H. Peng, "Analysis of Template Matching Prediction and Its Application to Parametric Overlapped Block Motion Compensation,"IEEE Int’l Symposium on Circuits and Systems, 2010.

[23] C. C. Chen, Y. W. Chen, F. Y. Yang, and W. H. Peng, "A Synthesis-Quality-Oriented Depth Refinement Scheme for MPEG Free Viewpoint Television (FTV)," IEEE Int’l Symposium on Multimedia, 2009.

[24] Y. W. Chen, T. W. Wang, Y. C. Tseng, W. H. Peng, and S. Y. Lee, "A Parametric Window Design for Overlapped Block Motion Compensation with Variable Block-size Motion Estimates,"IEEE Int’lWorkshop on Multimedia SignalProcessing, 2009.

[25] Y. W. Chen, C. H. Wu, C. L. Lee, T. W. Wang and W. H. Peng, " MB Mode with Joint Application of Template and Block Motion Compensations,"ITU-T SG16 WP3 and ISO/IEC JTC1/SC29/WG11 2nd meeting, JCTVC-B072, Geneva, CH, July 2010.

[26] Y. W. Chen, T. W. Wang, C. H. Chan, C. L. Lee, C. H. Wu, Y. C. Tseng, W. H. Peng, C. J.

Tsai, and H. M. Hang, " Description of video coding technology proposal by NCTU ", ISO/IEC JTC1/SC29/WG11 and ITU-T SG16 Q.6 1st meeting, JCT-VC –A123, Dresden, DE, April 2010.

[27] T.-F. Shen and C.-J. Tsai, “Dynamic Task Partitioning for Video Decoding on Heterogeneous Dual-Core Platforms,”Proc. of VLSI Design/CAD, Ken-Ting, Taiwan, Aug., 2008.

[28] K.-N. Su, H.-J. Ko, and C.-J. Tsai, “Java Runtime Environment Design for Embedded Multimedia Services,”Proc. of VLSI Design/CAD, Ken-Ting, Taiwan, Aug., 2008.

[29] M.-J. Wu, Y.-T. Chen, and C.-J. Tsai, “Hardware-assisted Syntax Decoding Model for Software AVC/H.264 Decoders,”Proc. of IEEE Int. Symposium on Circuit and System, Taipei, May 2009.

[30] K.-N. Su and C.-J. Tsai,“Fast Host Service Interface Design for Embedded Java Application Processor,”Proc. of IEEE Int. Symposium on Circuit and System, Taipei, May 2009.

[31] C.-N. Huwang, C.-Y. Bai, K.-N. Su, and C.-J. Tsai, “Dual-Core Java RE SoC with Embedded GUI Middleware,”Proc. of VLSI Design/CAD, Hua-Liang, Taiwan, Aug., 2009.

[32] C.-F. Hwang, K.-N. Su, and C.-J. Tsai,“Low-Cost Class Caching Mechanism for Java SoC,”Proc. of IEEE Int. Symposium on Circuit and System, Paris, May 2010.

已接受之論文

[1] C.-J. Tsai, T.-F. Shen, P.-C. Liao, “Dynamic Task Partition for Video Decoding on Heterogeneous Dual-core Platforms,”ACM Transactions on Embedded Computing Systems, Accepted Jan. 2011.

審稿中之論文

[1] Y.-R. Horng, Y.-C. Tseng, and T.-S. Chang, “VLSI architecture of real time HD1080p view synthesisengine,”IEEE Trans. on Circuits and Systems for Video Technology. (Under reviewing)

[2] Y.-C. Tseng, B.-H. Hsu, and T.-S.Chang,“A 124 Mpixels/secVLSIdesign for histogram-based joint bilateral filtering,” IEEE Trans. on Image Processing.

(Under reviewing)