h
impact ionization e
h
Fig.4.12 The range of oxide thickness and stress gate voltage where the hole current component is dominant in a fresh device and after breakdown. h or e represents hole current or electron current dominant regime, respectively.
Chapter 5 Conclusions
In short, this dissertation has discussed major SBD induced reliability issues in SOI CMOS with gate oxide in direct tunneling domain, among them the Vt hysteresis effects, excess low frequency noise, and breakdown hardness. Major contributions of each subject in this work are summarized as follows.
First, we have calculated the gate tunneling leakage current in ultra-thin oxide MOSFETs.
Two charge transport modes attributed to gate tunneling current is proposed. The gate tunneling current includes both source/drain tunneling current and substrate tunneling current.
A quantum charge transport mechanism is developed to study the Isd of the inversed carrier tunneling processes, and a classical charge transport mechanism is built to explore the Ib of the valance band electron tunneling processes. In addition, the combined Poisson and Schrodinger equations are solved self-consistently to simulate the accurate oxide electric field.
The C-V curve of ultra-thin gate oxide capacitance also can be calculated from the simulated results. The measured C-V and I-V of ultra-thin oxide can be fitted well by our proposed models.
Next, we reported the impact of breakdown position on hysteresis effects for ultra-thin oxide PD SOI MOSFETs. The excess substrate tunneling current of SBD PD SOI devices will modulate the substrate bias in specific operation conditions. As input signal is switching, the hysteresis effect of c-SBD PD SOI devices is enhanced. The dominant floating-body charging mechanism is valance band tunneling due to applied gate voltage. While output signal is changing, the hysteresis effect of e-SBD PD SOI devices is aggravated. The dominant floating-body charging mechanism is band-to-band tunneling when drain bias is large. Two SBD enhanced hysteresis modes in off-state CMOS have been evaluated and would be a serious reliability concern in ultra-thin oxide PD SOI circuits.
Then, the significance of soft breakdown position to the low frequency drain current noise in PD SOI nMOS devices has been identified. In high gate bias, the excess floating body noise would be enhanced if a breakdown path occurs at the channel. Large substrate leakage current of valance band electron tunneling in c-SBD not only affects the Vt hysteresis effect but also generates excess low frequency drain current noise source. This noise source correlates with the amplification by small white noise of substrate tunneling currents. The c-SBD enhanced excess noise would become an important reliability subject in ultra-thin oxide analog SOI devices.
Finally, in ultra-thin oxide pMOS, hole current instead of electron current is found to dominate breakdown progression. Enhanced breakdown hardness is observed with floating body. The enhanced breakdown evolution can be explained by the heating of channel holes and thus increased hole stress current during breakdown progression. The temperature rise of channel holes after oxide breakdown is caused by the valance electron tunneling through the BD path and the following electron-hole energy transfer process. Higher carrier temperature can produce a larger substrate bias effect on hole tunneling current by thermal excitation of holes into higher sub-bands. Numerical analysis of substrate bias effect on hole tunneling current is performed to support the proposed theory. The floating-body enhanced BD progression has large impact on the failure time of ultra-thin oxide SOI pMOS devices. All of these findings make SBD not just increase the tunneling leakage current but become a challenge of reliability issues in ultra-thin oxide PD SOI MOSFETs.
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Chapter 5
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