during electromigration

S. W. Liang, Y. W. Chang, T. L. Shao, and Chih Chen^a兲

Department of Material Science and Engineering, National Chiao Tung University, Hsin-chu, 30050 Taiwan, Republic of China

K. N. Tu

Department of Materials Science and Engineering, UCLA, Los Angeles, California 90095-1595 共Received 5 February 2006; accepted 23 May 2006; published online 13 July 2006兲

Effect of three-dimensional current distribution on void formation in flip-chip solder joints during electromigration was investigated using thermoelectrical coupled modeling, in which the current and temperature redistributions were coupled and simulated at different stages of void growth.

Simulation results show that a thin underbump metallization of low resistance in the periphery of the solder joint can serve as a conducting path, leading to void propagation in the periphery of the low current density region. In addition, the temperature of the solder did not rise significantly until 95%

of the contact opening was eclipsed by the propagating void. © 2006 American Institute of Physics.

关DOI:10.1063/1.2220550兴

Electromigration has become a critical reliability issue for high-density solder joints in flip-chip technology.^1,2 Electromigration-induced failures and mean time to failure 共MTTF兲 of flip-chip joints have been investigated for both eutectic SnPb and Pb-free solders.^3–10It was found that voids were formed inside the solder adjacent to the underbump metallization 共UBM兲,⁴ and propagated along the interface between the solder and the UBM, causing opening failure of the joints when the voids eclipsed the entire contact opening.

However, the mechanism of void nucleation and growth and especially the corresponding change of current distribution in the solder joint due to void formation are unclear. In particu-lar, it is unknown why some voids are formed at the periph-ery of the UBM opening under the dielectric, where the cur-rent density is low.^8,11In Blech structure of Al stripes, Tu et al. proposed that resistive vacancy might move to the low current density region to form voids due to the high gradient of current density, which was as high as 10¹⁰A / cm³.¹² How-ever, for flip-chip solder joint, the gradient is estimated to be only 1.33⫻10⁶A / cm³owing to its large dimension.⁸ There-fore, the growth of voids in the periphery of the UBM open-ing, which is located at the low current density region, may not be driven by the gradient of current density. In this letter, three-dimensional finite element method was employed to simulate the effect of void formation on redistribution of current density and temperature in a flip-chip solder joint, especially in the periphery area where a low-resistance thin-film UBM exists.

Three-dimensional 共3D兲 thermoelectrical coupled simu-lation was carried out by finite element analysis to find out the current density and temperature redistributions in our test samples.¹³The model used was a SOLID69 eight-node hexa-hedral coupled field element withANSYSsoftware. The elec-trical and thermal resistivities of the materials as well as the boundary conditions used in this modeling followed those of

our previous study.¹³ In our samples, the diameters of the passivation opening and the UBM opening were 85 and 120␮m, respectively. Figure 1共a兲 shows the cross-sectional view of the current density distributions before void growth when 0.28 A was applied to the bump. The Al trace, the UBM in the chip side, and the metallization in the substrate were ignored. It was found that the current crowded into the solder bump in the passivation opening. The current crowd-ing behavior near the entrance of the Al trace can be clearly demonstrated. The maximum current density reached 5.42

⫻10⁴A / cm², which is about 22 times higher than the aver-age value. It is proposed that this local high current density was responsible for the initial void formation due to flux divergence.^4,6Figure 1共b兲 illustrates the temperature distribu-tion before void formadistribu-tion. The maximum temperature inside the solder bump was 109.6 ° C; therefore, the increase in temperature due to Joule heating was only 9.6 ° C. The tem-perature was quite uniform inside the bulk of the solder.

In stage I, a semicylindrical void, 45.5␮m in diameter and 13.0␮m in height, was formed inside the solder near the entrance of the Al trace. The current redistributed due to void formation, and the maximum current density occurred in the solder near the upper left corner of the periphery of the UBM opening under the Al trace. As shown in Fig. 2共a兲, void

for-a兲Author to whom correspondence should be addressed; electronic mail:

[email protected]

FIG. 1. 共a兲 Cross-sectional view of current density distribution in solder joint before void formation;共b兲 corresponding cross-sectional view for tem-perature distribution.

APPLIED PHYSICS LETTERS 89, 022117共2006兲

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mation resulted in redistribution of current in two ways.

First, current may drift farther along the Al trace, passing the void, and entered the solder. Second, the current may drain down to the solder through the surrounding UBM/

intermetallic layer共IMC兲 layer. It is intriguing that the UBM/

IMC layers served as a current path, directing the current into the upper left corner of the periphery of the UBM open-ing. Since the UBM/IMC layers have much higher electromi-gration resistance,² voids are formed mainly inside the sol-der. It is clear that the solder on the left of the void has higher current density than that under the passivation open-ing. Therefore, voids may propagate toward the solder in the UBM periphery. Compared with that shown in Fig. 1, the maximum current density inside the solder has been reduced to 4.43⫻10⁴A / cm² due to void formation. On the other hand, the temperature inside the solder decreased slightly to 109.5 ° C, which was 0.1 ° C lower than that before void formation, as illustrated in Fig. 2共b兲. This may be attributed to the smaller crowding effect as a result of void formation.

Since the maximum current density occurred near the periphery of the UBM opening, we assume that the void propagates toward the left-hand-side periphery, as illustrated in Fig. 3共a兲. The void depleted 50% of the UBM opening, which is denoted as stage II. Since the UBM/IMC layers still serve as a current path, the void may be able to propagate to the edge of the solder bump. Therefore, we postulate that the growth of void in the low current density region under the periphery of the UBM opening is mainly attributed to current redistribution, not to the gradient of current density. The maximum current density inside the solder bump reduced further to 4.04⫻10⁴A / cm² due to void formation. Figure 3共b兲 shows the corresponding temperature distribution in the solder bump. The maximum temperature in the solder was 109.3 ° C, which was 0.2 ° C lower than that in stage II.

Again, this may be due to the smaller crowding effect in the solder joint at this stage. Although there was a slight increase

in temperature in the Al pad, the temperature inside the sol-der did not alter much at this stage. From the results reported by Gee et al.,¹¹the shape of the void may resemble a pan-cake shape for solder joints with thin-film UBM. In addition, due to the limitation of our simulation modeling, semicylin-drical voids were adopted in this study. However, whether it is circular, semicircular, or irregular remains unclear at this moment, and needs further experimental investigation.

The void was then assumed to propagate to fill 80.5% of the UBM opening, as shown in Fig. 4共a兲. It is denoted as stage III. The current entered the joints through a smaller contact area, causing an increase in maximum current den-sity. It rose to 8.70⫻10⁴A / cm², and almost the whole pas-sivation opening experienced current density higher than 1.0⫻10⁴A / cm². Therefore, void propagation would expe-dite in this stage. The maximum temperature in the solder bump increased to 109.4 ° C because of the higher current crowding effect at this stage, as shown in Fig. 4共b兲. In the absence of current flowing through the solder in the left-hand side of the joint, the temperature on the right-hand side was higher than that on the left-hand side. However, there was still no obvious temperature increase in the solder close to the entrance point of the current into the solder.

The solder in the passivation opening was completely depleted at this final stage, leaving a small amount of solder near the periphery of the UBM opening, as illustrated in Fig.

5共a兲. There was approximately 4.0% of contact area left for conducting the current at this stage. With further decrease in contact area, the maximum current density became 1.69

⫻10⁵A / cm². The UBM/IMC layers served as a conducting path to direct the current to the remaining solder. Hence, the remaining solder near the periphery of the UBM opening could be completely depleted and failure followed. Figure 5共b兲 shows the temperature distribution at this stage. The maximum temperature in the solder bump was 110.4 ° C, which was 0.8 ° C higher than that before void formation.

TABLE I. The simulated maximum current density inside the solder, the corresponding crowding ratio as well as the bump resistance at each stage.

Original

bump Stage I Stage II Stage III Stage IV

Void proportion共area%兲 0 28.8 50.0 80.5 96.0

Maximum current density inside solder

共A/cm²兲 5.42⫻10⁴ 4.43⫻10⁴ 4.04⫻10⁴ 8.70⫻10⁴ 1.69⫻10⁵

Bump resistance共m⍀兲 11.2 14.6 19.0 25.3 42.9

Maximum temperature inside solder共°C兲 109.6 109.5 109.3 109.4 110.4 FIG. 2. 共a兲 Cross-sectional view of current density distribution in solder

joint at stage I; 共b兲 corresponding cross-sectional view for temperature distribution.

FIG. 3. 共a兲 Cross-sectional view of current density distribution in solder joint at stage II; 共b兲 corresponding cross-sectional view for temperature distribution.

022117-2 Liang et al. Appl. Phys. Lett. 89, 022117共2006兲

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Our simulation also shows that bump resistance in-creased gradually in the first three stages, and then inin-creased rapidly in the final stage, as shown in Table I. Bump resis-tance was defined as the decrease in voltage between the entrance point of the Al trace into the Al pad共disk兲 and the junction point of the Cu line with the solder joint. In stage I, the bump resistance increased from 11.2 to 14.6 m⍀. It in-creased to 19.0 and 25.3 m⍀ in stages II and III, respec-tively. It rose to 42.9 m⍀ in stage IV. This increase in bump resistance may also enhance the local Joule heating effect.

However, no significant local Joule heating was found in the thermal simulation up to stage IV. This may be attributed to the fact that the major heating source was the Al trace.¹⁴In our model, the total resistance of the Al trace was about 1800 m⍀. Consequently, the increase in bump resistance was quite small compared with that of the Al trace. In addi-tion, the increase in bump resistance was mainly due to the following manner: owing to void formation, the current needed to drift farther in the Al pad共disk兲, and then flowed down to the solder bump. Therefore, the local Joule heating in the Al pad 共disk兲 increased when voids were formed.

Since there was good heat dissipation in the Si side, the increase in temperature due to void formation was quite small. Nevertheless, the increase might be higher when larger current was applied, since the overall Joule heating would be significantly higher at higher stressing current.

In summary, we have employed the 3D finite element method to simulate the current and temperature redistribu-tions due to the formation and propagation of a pancake-shape void in solder joints during electromigration. It is pro-posed that current redistribution is the main reason accounting for void formation and propagation, especially the propagation into the low current density region below the contact passivation. It is found that UBM provided a con-ducting path for current to go below the passivation, and it

directed the current to the periphery of the solder joint, which is in agreement with the experimental observation of void formation in those regions. Increase in temperature due to void formation was not significant since the major heat source was the Al trace and the applied current was as low as 0.28 A.

The authors would like to thank National Science Coun-cil of Taiwan of the Republic of China for the financial sup-port through Grant No. NSC 95-2218-E-009-022. In addi-tion, the assistance on simulation facility from the National Center for High-performance Computing共NCHC兲 in Taiwan is highly appreciated.

1International Technology Roadmap for Semiconductors, Semiconductor Industry Association, San Jose, CA, 2003.

2K. N. Tu, J. Appl. Phys. 94, 5451共2003兲.

10H. Ye, C. Basaran, and D. Hopkins, Appl. Phys. Lett. 82, 7共2003兲.

11L. Zhang, S. Ou, J. Huang, K. N. Tu, S. Gee, and L. Nguyen, Appl. Phys.

FIG. 4. 共a兲 Cross-sectional view of current density distribution in solder joint at stage III.;共b兲 corresponding cross-sectional view for temperature distribution.

FIG. 5. 共a兲 Cross-sectional view of current density distribution in solder joint at stage IV;共b兲 corresponding cross-sectional view for temperature distribution.

022117-3 Liang et al. Appl. Phys. Lett. 89, 022117共2006兲

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Infrared microscopy of hot spots induced by Joule heating in flip-chip SnAg solder joints under accelerated electromigration

S. H. Chiu, T. L. Shao, and Chih Chen^a兲

National Chiao Tung University, Department of Material Science and Engineering, Hsin-chu 300, Taiwan, Republic of China

D. J. Yao

National Tsing Hua University, Institute of Microelectromechanical System, Hsin-chu 300, Taiwan, Republic of China

C. Y. Hsu

National Tsing Hua University, Department of Power Mechanical Engineering, Hsin-chu 300, Taiwan, Republic of China

共Received 23 May 2005; accepted 31 October 2005; published online 11 January 2006兲

Joule heating effect in solder joints was investigated using thermal infrared microscopy and modeling in this study. With the increase of applied current, the temperature increased rapidly due to Joule heating. Furthermore, modeling results indicated that a hot spot existed in the solder near the entrance point of the Al trace, and it became more pronounced as the applied current increased.

The temperature difference between the hot spot and the solder was as large as 9.4 ° C when the solder joint was powered by 0.8 A. This hot spot may play an important role in the initial void formation during electromigration. © 2006 American Institute of Physics.

关DOI:10.1063/1.2151255兴

Electromigration has emerged as another reliability issue for high-performance and high-density flip-chip solder joints,^1,2and electromigration in solder joints has been stud-ied in recent years.^3–7The current crowding effect has been found to be responsible for the failure in the chip/anode side of the solder joint.^8,9The current used for typical accelerated electromigration tests ranges from 0.5 A to 2.2 A. Although whether a hot spot exists at the current crowding region is of interest, only a few studies have addressed the Joule heating effect in solder joints.^10–12However, there are still no experi-mental data to verify the temperature in the bump because the solder joints are completely surrounded by a chip, a sub-strate, and underfill; so no direct temperature measurement can be made to investigate the Joule heating effect inside the solder joints.

For this study, we used thermal infrared共IR兲 microscopy to measure the temperature distribution in the Al trace at various stressing conditions. Based on the experimental data, we constructed a finite element model to simulate the tem-perature distribution inside the solder bump during current stressing. Therefore, this study provides a deeper understand-ing of the Joule heatunderstand-ing effect inside the flip-chip solder joints during current stressing.

The fabrication procedure for the SnAg bumps can be found in our previous publication.⁸The thickness of the Si chip was 300␮m. The under-bump metallization 共UBM兲 consisted of 0.7␮^{m Cu, 0.3}␮m Cr–Cu, and 0.1␮m Ti. It is assumed that a layer-type Cu₆Sn₅ intermetallic compound 共IMC兲 of 1.4␮m thick grew in the interface of the UBM and the solder, whereas a layer-type Ni₃Sn₄IMC of 1.0␮^{m thick} formed in the interface of the pad metallization and the sol-der in the substrate side. The UBM and passivation openings were 120␮^{m and 85}␮m in diameter, respectively. The Al

trace on the chip side was 34␮m wide and 1.5␮^{m thick.}

The temperature increase inside the bumps when pow-ered by electric current was detected by thermal IR micros-copy, that had resolution of 0.1 ° C in temperature sensitivity and 2.8␮m in spatial resolution.

On the basis of the experimental results, a three-dimensional 共3D兲 simulation was carried out by finite ele-ment analysis. Only two of the solder bumps had electrical current passing through. The electrical and thermal resistivi-ties for the materials used in this modeling are listed in Table I. The effect of temperature coefficient of resistivity共TCR兲 was considered, and the TCR values for the metals are also listed in Table I. In addition, 3D coupled thermal-electric simulation was conducted to predict the steady-state tem-perature distribution using theANSYS software package de-veloped by ANSYS, Inc. The model used in this study was a

SOLID69eight-node hexahedral coupled field element. All the boundary conditions followed the experiment setup. The area

a兲Author to whom correspondence should be addressed; electronic mail:

[email protected]

TABLE I. Thermal conductivities, electrical resistivities, and temperature coefficients of resistivity for the materials used in the simulation model.

Material

Al trace 238.00 2.70 4.2

UBM共Ti+Cr/Cu+Cu兲 147.61 5.83 4.9

Note: The materials not given in electric resistivity are assumed to be electrical insulators.

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of the Si chip was 10.0 mm⫻6.0 mm and the thickness was 290␮m, whereas the bismaleimide triazine 共BT兲 substrate was 4.75 mm wide, 7 mm long, and 350␮^{m thick.}

Before the current stressing, calibration was performed on a hot plate maintained at 70 ° C. The temperature distri-bution without current stressing is shown in Fig. 1共a兲. The circuit of the Al trace can barely be seen since the Si sub-strate is transparent to IR radiation. Figure 1共b兲 shows the temperature increase for the Al trace in the package when stressed by 0.59 A at the ambient temperature of 70 ° C. The current path is indicated by two of the arrows in the figure.

There were two solder bumps located directly below the two circular Al pads/UBMs, as labeled in the figure. It is

There were two solder bumps located directly below the two circular Al pads/UBMs, as labeled in the figure. It is