第四章 應用對數系統設計快速正餘弦及指數函數產生器
4.4 電路分析與比較
我們在前面所提到的以對數系統為主的 Bhaskara I's 方程式以及快速正餘弦 產生器，可以看到 Bhaskara I's 方程式以及快速正餘弦產生器的面積、延遲時間 跟功率量測比較，在下方表4-4 的部分表示的是我們提出的以對數為主的兩種正 餘弦產生器的比較結果，並將這兩種方法的ADP 做計算，ADP 為延遲時間跟面 積的乘積，並且以快速正餘弦產生器為準，與 Bhaskara I's 方程式比較所節省的 成本。
Methods Area(𝜇𝑚2) Delay(ns) Power(mW) 使用對數系統的
座標轉換
1075908.57 86.02 214.90
直接*的 座標轉換
1337304.73 52.01 286.90
0.18𝜇m CMOS technology unitofarea:𝜇𝑚2 unitofdelay unitofpower:mW
表 4-4：兩種正餘弦產生器合成面積、延遲、功率量測、ADP 比較
表4-6 為所使用 python 產生出 1000000 筆隨機數據輸入至圖 4-1 跟圖 4-2 模型中，並依照其模型來進行誤差分析。
表4-6：快速正餘弦產生器誤差分析
在此章節我們使用對數系統來簡化運算的方法，做出了Bhaskara I's 方程式、
快速正餘弦產生器以及兩種方式的座標轉換，並將這些方程式及架構個別說明，
也將他們在相同的環境下做合成分析，也將本篇論文提出的Bhaskara I's 方程式、
快速正餘弦產生器來進行誤差分析與比較。
正弦 餘弦
最大誤差值 0.06657 0.00089
最小誤差值 ≅0 ≅0
最大誤差百分比 14.60% 10.90%
最小誤差百分比 0.0004% 0.0004%
平均誤差值 0.01108 9.98843 × 𝑒−5
參考文獻
[1] H. Kim, B. –G. Nam, J. –H. Sohn, J. –H. Woo, and H. –J. Yoo, “A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System”, IEEE Journal of Solid-State Circuits (JSSC), Vol. 41, No. 11, pp.2373-2381, Nov.
2006.
[2] Vojin G. Oklobdzija, “An Algorithmic and Novel Design of a Leading Zero Detector Circuit: Comparison with Logic Synthesis,” IEEE Transactions on Vera Large Scale Integration System, Vol. 2 , pp. 124 - 128, March 1994.
[3] J.-A. Pineiro, “Algorithm and architecture for logarithm, exponential, and powering computation,” IEEE Transaction on Computers, vol. 53, no. 9, pp.
1085–1096, Sep. 2004.
[4] J. A. Pineiro, M. D. Ercegovac, and J. D. Bruguera, “High-radix logarithm with selection by rounding: algorithm and implementation,” Journal of VLSI Signal Processing Systems, vol. 40, pp. 109–123, May 2005.
[5] D. K. Kostopoulos, “An algorithm for the computation of binary logarithms,”
IEEE Transaction on Computers, vol. 40, no. 11, pp. 1267–1270, Nov. 1991.
[6] M. J. Schulte and J. E. E. Swartzlander, “Hardware designs for exactly rounded elementary functions,” IEEE Transaction on Computers, vol. 43, no. 8, pp. 964–
973, Aug. 1994.
[7] P. T. P. Tang, “Table-lookup algorithms for elementary functions and their error analysis,” Proc. 10th Symp. Comput. Arithmetic, pp. 232–236. Jun. 1991.
[8] J. E. Stine and M. J. Schulte, “The symmetric table addition method for accurate function approximation,” Journal of VLSI Signal Procesing Systmes, vol. 21, pp.
167–177, Jun. 1999.
[9] M. J. Schulte and J. E. Stine, “Approximating elementary functions with symmetric bipartite tables,” IEEE Transactions on Computers, vol. 48, no. 8, pp.
842–847, Aug. 1999.
[10] K. Johansson, O. Gustafsson and L. Wanhammar, “Implementation of elementary functions for logarithmic number systems,” IET Computer & Digital Techniques, vol. 2, no. 4, pp. 295-304, July 2008.
[11] S. Paul, N. Jayakumar, and S. P. Khatri, “A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations,” IEEE Transactions on VLSI Systems, vol. 17, no. 2 pp. 269-277, February 2009.
[12] J. N. Mitchell, Jr., “Computer multiplication and division using binary logarithms,”
IRE Transanstions on Electronics Computers, vol. 11, no. 11, pp. 512–517, Nov.
1962.
[13] M. Combet, H. V. Zonneveld and L. Verbeek, “Computation of the base two
logarithm of binary numbers,” IEEE Transactions on Electronic Computers, vol.
14, no. 6, pp. 863–867, June 1965.
[14] S. L. SanGregory, R.E. Siferd, C. Brother, and D. Gallagher, “A fast, low-power logarithm approximation with CMOS VLSI implementation,” Proc. IEEE Midwest Symp. Circuits and Systems (MWSCAS), vol. 1, pp. 388-391, Aug. 1999.
[15] K. H. Abed and R. E. Siferd, “CMOS VLSI implementation of a low-power logarithmic converter,” IEEE Transactions on Computers, vol. 52, no. 11, pp.
1421–1433, Nov. 2003.
[16] H. Kim, B. –G. Nam, J. –H. Sohn, J. –H. Woo, and H. –J. Yoo, “A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System”, IEEE Journal of Solid-State Circuits (JSSC), Vol. 41, No. 11, pp.2373-2381, Nov.
2006.
[17] T. –B. Juang, S. –H. Chen and H. –J. Cheng, “A lower-error and ROM-free logarithmic converter for digital signal processing applications,” IEEE Transactions on Circuits and Systems II, vol. 56, no. 12, pp. 931-935, December 2009.
[18] 李穎仁，莊作彬，2017，具有共時錯誤偵測能力之對數運算器之設計，國立 屏東大學資訊工程學系碩士論文。
[19]Tso-Bing Juang, Han-Lung Kuo and Kai-Shiang Jan,“Lower-Error and Area-Efficient Antilogarithmic Converters with Bit-Correction Schemes,” Journal of the Chinese Institute of Engineers, Vol. 39, No. 1, pp. 57-63, Jan. 2016T. –B.
[20] I.Newton, The Method of Fluxions and Infinite Series. UK:Henry Woodfall,1736.
[21] C. Wang, X. Zhou and Y. Ma, "Based on the physical system of the analysis and research in Newton's method," 2019 Chinese Control And Decision Conference (CCDC),Nanchang, China, 2019, pp. 206-211.
[22] 林琮翊，莊作彬，2018，使用對數系統加速 CNN 電路之設計，國立屏東大 學資訊工程學系碩士論文。
[23] R.C.GUPTA. (1967). BHASKARA I’S APPROXIMATION TO SINE. 1-16.
[24] Evans, P. R. (2001). Rotations and rotation matrices. 1-5.