第五章 電路分析與結果
5.7 傳統霍納法以RS(7,3)的分析
圖46. 傳統霍納法以RS(7,3)的分析結果
由圖46.可以看到傳統霍納法以RS(7,3)中clk最大可到達923.36MHz 5.8 傳統霍納法以RS(204,188)的分析結果
傳統霍納法以RS(204,188)的分析結果如圖47
由圖47.可以看到傳統霍納法以RS(204,188)中clk最大可到達589.97MHz
圖47. 傳統霍納法以RS(204,188)的分析結果
第六章 結論
本論文的研究方向改良RS Code中症狀子的計算速度和硬體化，在提升 速度上本論文有三個研究方向，第一是將接收到的訊息多項式進行分群，第 二把多項式改良成霍納法的形式，最後，再使用p多項式進行運算差值量法。
針對本論文中提出的方法與傳統的霍納法的比較與分析，發現傳統的霍納 法電路執行速度會受到乘法模組的影響，m的值越大，速度會越慢，而在本 論文的方法，較不會受限於m的大小，在分析的結果中執行的延遲最大在於 位移模組把值傳到pipeline模組中的過程，m越大時，在這兩個模組傳遞中，
延遲不會在往上提升。針對m=3和8之設計上，其設計法一樣將輸入以三個 為一組進行傳遞，經由比較clk的時間來分析速度如表3，整體計算症狀子效 能，比傳統霍納法實作電路改進約32%的速度。
表3. 分析結果比較
傳統霍納法 本論文方法 提升
m=3 923.36MHz 1084.6MHz 16%
m=8 589.97MHz 868.06MHz 32%
參考文獻
[1] Stephen B. Wicker,“Error Control systems for Digital Communication and Storage,” Prentice hall international, Inc.
[2] S. B. Wicker and V. K. Bhargava, Reed–Solomon Codes and Their Application.New York: IEEE Press, 1994.
[3] Eklund, R. B. Marks, K. L. Stanwood, and S. Wang, “IEEE standard 802.16:
A technical overview of theWirelessMAN air interface for broadband wireless access,” IEEE Commun. Mag., vol. 40, no. 6, pp. 98–107, 2002.
[4] S. B. Wicker, Error Control systems for Digital Communication and Storage, Englewood Cliffs, N.J.: Prentice-Hall, 1994.
[5] Yeh,C.S.,Reed, I. S., and Troung, T.K., “Systolic Multipliers for Finite Fileds𝐺𝐹(2𝑚), ”IEEE Trans. Computers. Papers C-33, 357-360, 1984.
[6] X. Tang, and S. Wang “A Low Hardware Overhead Self-Diagnosis Technique Using Reed-Solomon Codes for Self-Repairing Chips,” IEEE Trans. Computers, vol. 59, no. 10, pp.1309-1319, 2010.
[7] Lin, T. C., Truong, T. K., and Chen, P. D., "A fast algorithm for the syndrome calculation in algebraic decoding of Reed–Solomon codes,"
IEEE Trans. Commun. Papers 5(12), 2240-2244 2009.
[8] Sergei V. Fedorenko, and Peter V. Trifonov, “Finding Roots of Polynomials Over Finite Fields,” IEEE Trans. Commun., vol. 50, pp. 1709–1711, 2002.
[9] T. K. Truong, J. H. Jeng, and I. S. Reed, “Fast algorithm for computing the roots of error locator polynomials up to degree 11 in Reed–Solomon decoders,” IEEE Trans. Commun., vol. 49, pp. 779–783, 2001.
[10] E. Costa , S. V. Fedorenko and P. V. Trifonov, “On computing the syndrome polynomial in Reed–Solomon decoder,” Euro. Trans. Telecom., vol. 15, no. 4, pp.337 -342, 2004.
[11] Berlekamp, E. R., [Algebraic Coding Theory]. New York: McGraw-Hill, 1968.
附錄
以(7,3, 5) RS碼，完整的Verilog code:
module ok(cls,clk,clk3,data,S0,S1,S2,S3,L0,L1,L2,SF0,SF1,SF2,count1,LST);
input clk;
output clk3,cls;
input [2:0] data;
output [2:0] S0,S1,S2,S3;
output [2:0] L0,L1,L2;
output [2:0] SF0,SF1,SF2,LST;
output [1:0] count1;
reg [2:0] reg0,reg1,reg2,ll0,ll1,ll2;
reg [1:0] count;
reg [2:0] ccls;
wire [2:0] w0,w1,w2,w3;
wire [2:0] wL0,wL1,wL2;
reg clst;
assign cls=clst;
always@(posedge clk) begin
always@(posedge clk) begin
reg0<=data;
reg1<=reg0;
reg2<=reg1;
end
always@(posedge clk3, negedge cls) begin
madeL LM0(reg1,3’b001,3’b001,3’b001,ll0,ll1,ll2,cls,clk3,wL0,w0,SF0); // alpha1, alpha2, alpha3 madeL LM1(reg1,3’b010,3’b100,3’b011,ll0,ll1,ll2,cls,clk3,wL1,w1,SF1);
madeL LM2(reg1,3’b100,3’b110,3’b101,ll0,ll1,ll2,cls,clk3,wL2,w2,SF2);
pmode LM3(reg1,3’b011,3’b100,3’b111,wL0,wL1,wL2,SF2,cls,clk3,w3,LST); //alpha1, alpha3, z assign L0=wL0;
assign L1=wL1;
assign L2=wL2;
assign S0=w0;
assign S1=w1;
assign S2=w2;
assign S3=w3;
assign clk3=!(!count[0]&count[1]);
always@(negedge clk) begin
assign count1=count;
endmodule module mul(a,b,c);
input [2:0]a,b;
output [2:0]c;
wire [2:0] w1,w2;
assign w1={a[2],a[2],a[2]}&b;
assign w2={a[1],a[1],a[1]}&b^{1’b0,w1[2],w1[2]}^{w1[1],w1[0],1’b0};
assign c={a[0],a[0],a[0]}&b^{1’b0,w2[2],w2[2]}^{w2[1],w2[0],1’b0};
endmodule
module madeL(data,alpha1,alpha2,alpha3,d1,d2,d3,cls,clk3,Lx,Sx,SFx);
input [2:0] alpha1, alpha2, alpha3, d1, d2, d3, data;
input cls,clk3;
output [2:0] Lx,Sx,SFx;
reg [2:0] St;
reg [2:0] Sx;
wire [2:0] w0, w1,aw0,aw1,w0t,w1t,w2t;
assign aw1=alpha2;
assign aw0=alpha1;
mul u1(aw1,d3,w1);
mul u0(aw0,d2,w0);
assign Lx=w1^w0;
assign w0t=Lx^d1^St;
assign SFx=Lx^d1;
mul Syn(w0t,alpha3,w1t);
mul Syn1(w0t,alpha1,w2t);
always@(negedge cls) begin
Sx=w2t^data;
end
always@(posedge clk3, negedge cls) begin
module pmode(data,alpha1,alpha3,Z,L0,L1,L2,SFx,cls,clk3,Sx,LST);
input cls, clk3;
input [2:0] data, alpha1, alpha3, Z, L0, L1, L2, SFx;
output[2:0] Sx,LST;
wire [2:0] ztemp,w0t,w1t,w2t;
reg [2:0] St;
reg [2:0] Sx;
assign ztemp= (L0&{3{Z[0]}}) ^ (L1&{3{Z[1]}})^ (L2&{3{Z[2]}}) ^ SFx;
assign w0t=ztemp^St;
mul Syn(w0t,alpha3,w1t);
mul Syn1(w0t,3’b011,w2t);
//assign Sx=w0t;
assign LST=w0t;
always@(negedge cls) begin
Sx=w2t^data;
end
always@(negedge clk3, negedge cls) begin
以(204,188, t=8)RS 碼，完整的 Verilog code:
module
ok(cls,clk,clk3,data,S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,L0,L1,L2,L3,L4,L5,L6,L7,SF7);
parameter size=8;
input clk;
output clk3,cls;
input [size-1:0] data;
output [size-1:0] S0,S1,S2,S3,S4,S5,S6,S7;
output [size-1:0] S8,S9,S10,S11,S12,S13,S14,S15;
output [size-1:0] L0,L1,L2,L3,L4,L5,L6,L7;
output [size-1:0] SF7;
wire [size-1:0] SF0,SF1,SF2,SF3,SF4,SF5,SF6;
//output [1:0] count1;
reg [size-1:0] reg0,reg1,reg2,ll0,ll1,ll2;
reg [1:0] count;
reg [size-1:0] ccls;
wire [size-1:0] w0,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15;
wire [size-1:0] wL0,wL1,wL2,wL3,wL4,wL5,wL6,wL7;
reg clst;
assign cls=clst;
always@(posedge clk) begin
if (ccls==8'hd0) begin
end
always@(posedge clk) begin
reg0<=data;
reg1<=reg0;
reg2<=reg1;
end
always@(posedge clk3, negedge cls) begin
madeL LM0(reg1,8'b00000001,8'b00000001,8'b00000001,ll0,ll1,ll2,cls,clk3,wL0,w0,SF0);//0 madeL LM1(reg1,8'b00000010,8'b00000100,8'b00001000,ll0,ll1,ll2,cls,clk3,wL1,w1,SF1);//1 madeL LM2(reg1,8'b00000100,8'b00010000,8'b01000000,ll0,ll1,ll2,cls,clk3,wL2,w2,SF2);//2 madeL LM3(reg1,8'b00001000,8'b01000000,8'b00111010,ll0,ll1,ll2,cls,clk3,wL3,w3,SF3);//3 madeL LM4(reg1,8'b00010000,8'b00011101,8'b11001101,ll0,ll1,ll2,cls,clk3,wL4,w4,SF4);//4 madeL LM5(reg1,8'b00100000,8'b01101100,8'b00100110,ll0,ll1,ll2,cls,clk3,wL5,w5,SF5);//5 madeL LM6(reg1,8'b01000000,8'b10101101,8'b00101101,ll0,ll1,ll2,cls,clk3,wL6,w6,SF6);//6 madeL LM7(reg1,8'b10000000,8'b10001110,8'b01110101,ll0,ll1,ll2,cls,clk3,wL7,w7,SF7);//7
pmode LM8(reg1,3'b011,3'b100,3'b111,wL0,wL1,wL2,SF2,cls,clk3,w3);
pmode LM9(reg1,8'h1d,8'hc9,8'h9d,wL0,wL1,wL2,wL3,wL4,wL5,wL6,wL7,SF7,cls,clk3,w8);
pmode LM10(reg1,8'h3a,8'h06,8'hba,wL0,wL1,wL2,wL3,wL4,wL5,wL6,wL7,SF7,cls,clk3,w9); //alpha1, alpha3, z
pmode LM11(reg1,8'h74,8'h30,8'hf4,wL0,wL1,wL2,wL3,wL4,wL5,wL6,wL7,SF7,cls,clk3,w10);
pmode LM12(reg1,8'he8,8'h9d,8'h68,wL0,wL1,wL2,wL3,wL4,wL5,wL6,wL7,SF7,cls,clk3,w11);
pmode LM13(reg1,8'hcd,8'h9c,8'h4d,wL0,wL1,wL2,wL3,wL4,wL5,wL6,wL7,SF7,cls,clk3,w12);
pmode LM14(reg1,8'h87,8'h94,8'h07,wL0,wL1,wL2,wL3,wL4,wL5,wL6,wL7,SF7,cls,clk3,w13);
pmode LM15(reg1,8'h13,8'hd4,8'h93,wL0,wL1,wL2,wL3,wL4,wL5,wL6,wL7,SF7,cls,clk3,w14);
pmode LM16(reg1,8'h26,8'hee,8'ha6,wL0,wL1,wL2,wL3,wL4,wL5,wL6,wL7,SF7,cls,clk3,w15);
//pmode LM3(reg1,3'b011,3'b100,3'b111,wL0,wL1,wL2,SF2,cls,clk3,w3); //alpha1, alpha3, z
assign L0=wL0;
assign L1=wL1;
assign L2=wL2;
assign L3=wL3;
assign L4=wL4;
assign L5=wL5;
assign L6=wL6;
assign L7=wL7;
assign S0=w0;
assign S1=w1;
assign S2=w2;
assign S3=w3;
assign S4=w4;
assign S5=w5;
assign S6=w6;
assign S7=w7;
assign S8=w8;
assign S9=w9;
assign S10=w10;
assign S11=w11;
assign S12=w12;
assign S13=w13;
assign S14=w14;
assign S15=w15;
assign clk3=!(!count[0]&count[1]);
always@(negedge clk) begin
//assign count1=count;
endmodule
module mul (a,b,c);
input [7:0] a,b;
output [7:0] c;
wire [7:0] w0,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;
assign w0={a[7],a[7],a[7],a[7],a[7],a[7],a[7],a[7]}&b;
assign
assign
module madeL(data,alpha1,alpha2,alpha3,d1,d2,d3,cls,clk3,Lx,Sx,SFx);
parameter size=8;
input [size-1:0] alpha1, alpha2, alpha3, d1, d2, d3, data;
input cls,clk3;
output [size-1:0] Lx,Sx,SFx;
reg [size-1:0] St;
reg [size-1:0] Sx;
wire [size-1:0] w0, w1,aw0,aw1,w0t,w1t,w2t;
assign aw1=alpha2;
assign aw0=alpha1;
mul u1(aw1,d3,w1);
mul u0(aw0,d2,w0);
assign Lx=w1^w0;
assign w0t=Lx^d1^St;
assign SFx=Lx^d1;
mul Syn(w0t,alpha3,w1t);
mul Syn1(w0t,alpha1,w2t);
always@(negedge cls) begin
Sx=w2t^data;
end
always@(posedge clk3, negedge cls) begin
module pmode(data,alpha1,alpha3,Z,L0,L1,L2,L3,L4,L5,L6,L7,SFx,cls,clk3,Sx);
parameter size=8;
input cls, clk3;
input [size-1:0] data, alpha1, alpha3, Z, L0, L1, L2,L3,L4,L5,L6,L7,SFx;
output[size-1:0] Sx;
wire [size-1:0] ztemp,w0t,w1t,w2t;
reg [size-1:0] St;
reg [size-1:0] Sx;
assign ztemp= (L0&{size{Z[0]}}) ^ (L1&{size{Z[1]}})^ (L2&{size{Z[2]}})^(L3&{size{Z[3]}}) ^ (L4&{size{Z[4]}})^ (L5&{size{Z[5]}})^(L6&{size{Z[6]}}) ^ (L7&{size{Z[7]}})^ SFx;
assign w0t=ztemp^St;
mul Syn(w0t,alpha3,w1t);
mul Syn1(w0t,alpha1,w2t);
//assign Sx=w0t;
//assign LST=w0t;
always@(negedge cls) begin
Sx=w2t^data;
end
always@(negedge clk3, negedge cls) begin
module syndH(clk,d,s0,s1,s2,s3);
input clk;
input [2:0] d;
output[2:0]s0,s1,s2,s3;
SX u1 (clk,d,3'b001,s0);
SX u2 (clk,d,3'b010,s1);
SX u3 (clk,d,3'b100,s2);
SX u4 (clk,d,3'b011,s3);
endmodule
module mul(a,b,c);
input [2:0]a,b;
output [2:0]c;
wire [2:0] w1,w2;
assign w1={a[2],a[2],a[2]}&b;
assign w2={a[1],a[1],a[1]}&b^{1'b0,w1[2],w1[2]}^{w1[1],w1[0],1'b0};
assign c={a[0],a[0],a[0]}&b^{1'b0,w2[2],w2[2]}^{w2[1],w2[0],1'b0};
endmodule
module SX(clk,data,alpha,So);
input [2:0] alpha;
input clk;
reg [2:0] So;
wire [2:0] w0,w1;
assign w0=data^So;
mul u0(w0,alpha,w1);
always@(posedge clk) begin
So=w1;
end
endmodule
(204,188, t=8) RS 碼，霍納法完整 verilog code:
module syndH(clk,d,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15);
parameter size=8;
input clk;
input [size-1:0] d;
output[size-1:0]s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15;
SX u0 (clk,d,8'b00000001,s0);
SX u1 (clk,d,8'b00000010,s1);
SX u2 (clk,d,8'b00000100,s2);
SX u3 (clk,d,8'b00001000,s3);
SX u4 (clk,d,8'b00010000,s4);
SX u5 (clk,d,8'b00100000,s5);
SX u6 (clk,d,8'b01000000,s6);
SX u7 (clk,d,8'b10000000,s7);
SX u8 (clk,d,8'b00011101,s8);
SX u9 (clk,d,8'b00111010,s9);
SX u10 (clk,d,8'b01110100,s10);
SX u11 (clk,d,8'b11101000,s11);
SX u12 (clk,d,8'hcd,s12);
SX u13 (clk,d,8'h87,s13);
SX u14 (clk,d,8'h13,s14);
SX u15 (clk,d,8'h26,s15);
endmodule
module mul (a,b,c);
input [7:0] a,b;
output [7:0] c;
wire [7:0] w0,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;
assign w0={a[7],a[7],a[7],a[7],a[7],a[7],a[7],a[7]}&b;
assign
3[4],w3[3],w3[2],w3[1],w3[0],1'b0};
module SX(clk,data,alpha,So);
parameter size=8;
input [size-1:0] alpha;
input clk;
input [size-1:0] data;
output [size-1:0] So;
reg [size-1:0] So;
wire [size-1:0] w0,w1;
assign w0=data^So;
mul u0(w0,alpha,w1);
always@(posedge clk) begin
So=w1;
end
endmodule
Dev C++ 軟體模擬的程式碼:
#include <cstdlib>
#include <iostream>
#include <math.h>
using namespace std;
int m=3;
int t=2;
unsigned int p;
unsigned int GFM(unsigned int a, unsigned int b) {
unsigned mask=pow(2,m)-1;
for(int i=m-1;i>=1;i--) {
c=c^a*((b>>i)&0x01);
c=((c<<1)&mask)^(p*((c>>(m-1))&0x01));
return c;
}
unsigned int powa(unsigned int alpha, int pv) {
int main(int argc, char *argv[]) {
} //--for i
cout << "---" << endl;
for(int j=0;j<2*t;j++){
A[j]=A[j]^a[0];
// cout << "S" << j << "=" << A[j] << endl;
}
system("PAUSE");
return EXIT_SUCCESS;
}