3-1-1.Instruments
(1) Microscope, Hot chuck, Probe station, as shown in Fig. 3-1-1 .
(2) Agilent 4284A, Agilent 4156C, Anilent E5250 (Switch), as shows in Fig. 3-1-2 (3) Agilent 4294A , Agilent B2201A (Switch) and Keithley 4200-SCS as shown in
Fig. 3-1-3.
(4) TTP-6 Probe Station as shown in Fig. 3-1-4.
(5) Software of measurement
ICS (Interactive Characterization Software) Use the Software to get:
VDS-IDS
VGS-IDS (Linear Region) VGS-IDS (Saturation Region) VGS-Gm
Note： VDS: Drain Voltage IDS: Drain current VGS: Gate Voltage IGS: Gate current Gm: VGS - IDS max slope
3-1-2.Set up instruments for I-V and C-V
The current – voltage characteristic measurement of thin film transistor devices was performed by 4200-SCS semiconductor characterization system with source grounded and body floating.
The electrical test setup of 4200-SCS semiconductor characterization system, illustrated at Fig.3.1.3, a probe station situated inside a dark box. The ground probe station is furnished with an electrically isolated, water-cooled thermal chuck. The chuck is controlled by Temptronic TPO315A thermal controller, which can operate temperature from 25℃ to 300℃. A Keithley 4200-SCS semiconductor characterization system provides I-V measurement, bias for BTS. The 4200-SCS is connected to B2201A low leakage switch mainframe, and then link to dark box.
The current-voltage (I-V) characteristics measurements were gotten by using n-TFT and p-TFT structure with Keithley 4200-SCS semiconductor characterization system. Keithley 4200-SCS can measure the minimum leakage current: 1f (A).
3-2. Methods of Device Parameter Extraction 3-2-1 Determination of the threshold voltage
Plenty ways are used to determinate the threshold voltage which is the most important parameter of semiconductor devices. The method to determinate the threshold voltage in some thesis is the constant drain current method that the voltages at a normalized drain current NID is taken as the threshold voltage. This technique is adopted in most studies of TFTs. It can give a threshold voltage close to that obtained by the complex linear extrapolation method. Typically, the threshold
current ⎟⎟ to extract the threshold voltage of TFTs. However, the method to determinate the
threshold voltage in my thesis is the linear extrapolation method. It is one of the most common threshold voltage measurement techniques. With the drain current measured as a function of gate voltage at a low drain voltage of typically 50-100 mV to ensure operation in the linear MOSFET region. According to equation︰
(3-1) (3-2)
the drain current is zero for [ VGS-VT-0.5VDS]=0. But Eq. (3-2) is valid only above threshold. The drain current is not zero below threshold and approaches zero only asymptotically. Hence the ID versus VGS curve is extrapolated to ID=0, and the threshold voltage is determined from the extrapolated or intercept gate voltage VGS by
(3-3)
Eq. (3-3) is strictly only valid for negligible series resistance. Fortunately series resistance is usually negligible at the low drain currents where threshold voltage measurements are made, but the resistance can be appreciable in LDD devices. The linear extrapolation technique can also be used for threshold voltage measurements of depletion-mode or buried channel MOSFET. The ID-VGS curve deviates from a straight line at gate voltages below VT due to sub-threshold currents and above VT due to series resistance and mobility degradation effects. It is common practice to find the point of maximum slop on the ID-VGS curve by a maximum in the transconductance extrapolate to ID=0. According to Eq. (3-3), VT=0.6V for this device. The linear extrapolation method is sensitive to series resistance and mobility degradation.
]
3-2-2 Determination of the field-effect mobility
The field-effect mobility (μFE) is determined from the transconductance gm at low drain voltage. The transfer characteristics of poly-Si TFTs are similar to those of conventional MOSFETs, so the first order I-V relation in the bulk Si MOSFETs can be applied to the poly-Si TFTs, which can be expressed as
(3-4) Where
Cox is the gate oxide capacitance per unit area, W is channel width, L is channel length, VTH is the threshold voltage.
If VD is much smaller than VG-VTH (i.e. VD << VG-VTH) and VG > VTH, the drain current can be approximated as:
(3-5)
The transconductance is defined as
(3-6) Therefore, the field-effect mobility can be obtained by
(3-7)
3-2-3Determination of on/off current ratio
On/Off ratio is another important factor of TFTs. High On/Off ratio represents not only large turn-on current but also small off current (leakage current). It affects the bright and dark states of TFT screens directly. The leakage mechanism in poly-Si
( ) ⎥⎦⎤
TFTs is much different from conventional MOSFETs since the channel layer of poly-Si TFTs is composed of polycrystalline. A large amount of trap densities in grain structure serve as lots of defect states in energy band gap to enhance tunneling effect. Therefore, the leakage current due to trap-assisted tunneling effect is much larger in poly-Si TFTs than in the single crystal MOSFETs. There are many methods to specify the on and off current. The easiest one is to define the maximum current as on current and the minimum leakage current as off current while drain voltage equal to 0.1V.
3-2-4 Determination of the subthreshold swing
Sub-threshold swing S.S (V/dec) is a typical parameter to describe the control ability of gate toward channel. It is defined as the amount of gate voltage required to increase/decrease drain current by one order of magnitude. The sub-threshold swing should be independent of drain voltage and gate voltage. However, in reality, the sub-threshold swing might increase with drain voltage due to short-channel effects such as charge sharing, avalanche multiplication, and punch through-like effect. The sub-threshold swing is also related to gate voltage due to undesirable factors such as serial resistance and interface state. In this experiment, the sub-threshold swing is defined as one-second of the gate voltage required to decrease the threshold current by three orders of magnitude. The threshold current is specified to be the drain current when the gate voltage is equal to the threshold voltage.
3-2-5
Determination of the trap densityAs described in Eq. (1-3), the grain boundary potential barrier height VB is related to the carrier concentrations inside the grain and the trapping states located at
grain boundaries. Based on this consideration, the amount of trap state density Nt can be extracted from the current-voltage characteristics of poly-Si TFTs. As proposed by Levinson and Proano method [3-1] [3-2], the I-V characteristics including the trap density can be obtained by replacing Eq. (1-3) and Eq. (1-11) into Eq.(3-12):
…….(3-8)
This equation had been further corrected by Proano et al. by considering the mobility under low gate bias . It is found that the behavior of carrier mobility under low gate bias can be expressed more correctly by using the flat-band voltage VFB instead of the threshold voltage VTH. Moreover, a better approximation for channel thickness tch in an undoped material is given by defining the channel thickness as the thickness at which 80 percent of the total charge resides. Therefore, by solving the Poisson’s equation, the channel thickness is given by
………(3-9)
The drain current of poly-Si TFTs then should be expressed as
………..(3-10)
The grain-boundary trap state density then can be obtained from the slope of the curve ln[ID/(VG-VFB)] versus (VG-VFB)-2 as in Fig. 3-2-1 [3-1], where the flat-band
voltage (VFB) is defined as the gate voltage that yields the minimum drain current from the transfer characteristic with linear region. Finally, the grain-boundary trap state density can be determined from the square root of the slope:
………..(3-11)
Reference
[3-1] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M.
Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,”J. Appl. Phys.,vol. 53, no. 2,pp.1193-1202,Feb. 1982.
[3-2] R. E. Proano, R. S. Misage, and D. G. Ast, “Development and electrical properties of undoped polycrystalline silicon thin-film transistor,” IEEE Trans.
Electron Devices, vol. 36, no. 9, pp. 1915-1922, Sep. 1989.
Chapter 4
Results and Discussion
4-1. The Degradation of P-channel TFT under pulse 4-1-1.The pulse effects
Fig. 4-1-1(a) shows the dynamic stress condition. The rectangular pulse with an amplifier of 0V to -15V was applied to the gate electrode and the drain voltage was fixed at -15V. The gate width and length of device are 128um and 8um, respectively. The stress frequencies are 1Hz and 10 KHz with duty ratio of 50%. The waveform is shown in Fig. 4-1-1(b). Fig. 4-1-2 shows that the output characteristics measured before and after the stress for 1000 seconds under low-frequency operation as shown in the Fig. 4-1-2(a) and high-frequency operation as shown in the Fig.
4-1-2(b). From figures, it is clearly seen that the stress frequency dependence of the threshold-voltage (Vth) shift after stress. At a low frequency, as shown in Fig.
4-1-3(a), the maximum and minimum temperature difference between the turn-on and turn-off states of TFT is obvious [4.1].This finding indicates that low-frequency operation leads to a more severe degradation on threshold-voltage. Because the joule heating is proportional to the time, it may be attributed to the time of current flow in the channel. As the stress frequency was increased, the maximum and minimum temperatures approached each other that result in the degradation of threshold-voltage shift no longer changing with increasing frequency, as shown in Fig. 4-1-3(b). In order to prove that the degradation depends upon the time of the current flow in the channel, the duty ratio was changed but the stress frequency was still fixed at 1Hz. The gate width and length of device are 10um and 4.5um, respectively. One of the duty ratios of stress is ten percent, and the other is ninety
percent. The larger duty ratio means the time of the current flow in the channel is longer. Fig. 4-1-4 shows the more serious degradation of threshold-voltage occurs in the larger duty ratio indeed. Therefore, the degree of degradation of threshold-voltage is closely related to the current flow time in the channel. The degradation of threshold-voltage associated with the joule heating will be investigated in the next section.
4-1-2. The temperature effects
Fig. 4-1-5 shows the transfer characteristics of the TFT before and after ac stress at different temperatures. The gate voltage is varied with the amplifier of 0V to -15V and the source/drain voltage is fixed at 0V. The temperatures are 300k and 400k. It is observed that the threshold-voltage shifts seriously at 400k. The phenomenon may be attributed to the temperature. Fig. 4-1-6 shows the degradation effect of TFT at 173k, 300k, 400k with the stress frequency of 1Hz and the duty ratio of 90%. The drain voltage was fixed at -15V, and the pulse of 0V to -15V was applied to the gate electrode. It is observed that the degradation of threshold-voltage is about 103% at 400K, which degradation of Vth is the more serious than that at 173k and 300k. Because the more thermal energy can be provided at the higher temperature, it causes the more serious degradation of threshold-voltage. In addition, comparing the degradations of Vth in Fig. 4-1-5(b) and Fig. 4-1-6(c), the threshold-voltage shift is also more serious as drain electrode is biased with the -15V.
This is because the higher temperature exists in the channel due to the extra current flow. Thus, drain voltage is the mainly factor in this degradation phenomenon [4.2].
It has been reported that the degradation of threshold-voltage can be attributed to the fixed charge in the oxide and the dangling-bond in interface of the oxide and the
silicon film. However, the degradation mechanism for poly-Si may be different from MOSFETs because of the grain boundaries in the channel regions. In order to investigate the effects of the grain boundaries in the poly-Si during stress, the grain-boundary trap-state densities (Ntrap) before and after stress were estimated by the method in the 3-2-5 section. The trap density of grain-boundary was extracted from transfer characteristics at T= 400K. Fig.4-1-7 shows that the trap density of grain-boundary is increased after stress, indicating that the generation of Ntrap plays an important role in the degradation for poly-Si. Fig. 4-1-8 describes the relation between the generation of grain-boundary traps and the threshold-voltage shift. It explains the linear fit of the grain-boundary trap generation versus the threshold-voltage shift at the beginning. The degradation of threshold-voltage is more serious as the grain-boundary trap density increases. However, the increment of the trap density is slowed down as threshold-voltage shift is increased to a value. In addition to the grain-boundary trap-state generation as mentioned above, we suggest that the interface trap states at the poly-Si/SiO2 interface are also generated in the poly-Si during ac stress. Fig. 4-1-9 presents the relation between the subthreshold-swing degradation and the threshold-voltage shift. The subthreshold-swing has been reported to be closely related to the trap states located near the midgap, which originated from dangling bonds [4.3]. Hence, the ac stress causes the weak-bonds broken at the poly-Si/SiO2 interface, and it generates more dangling bonds resulting in the increase of interface trap states. By neglecting the depletion capacitance in the active layer, the effective interface-trap density (Nit) near the poly-Si/SiO2 interface can be evaluated from the subthreshold-swing(S)[4.4].
Fig. 4-1-10 describes the relationship between the interface-trap generation and the threshold-voltage shift. It is clearly seen that the linear fit of the interface-trap generation versus the threshold-voltage shift. The degradation of threshold-voltage is more serious as the interface-trap generation increases. Therefore, the trap-state generation includes both the traps in grain boundaries and at the poly-Si/SiO2 interface for poly-Si after ac stress. In addition, as the TFT is at on-state, the current flow in the channel leads to the temperature increasing. The Si-H bonds existing in the grain-boundary and the interface may be broken as the temperature increases to a value. The released hydrogen species from the grain-boundaries and the interface diffuse into the oxide and react with SiO2, forming OH groups bounded to oxide Si atoms and leaving positive fixed oxide charges as negative bias was applied. This phenomenon is the so-called the negative bias temperature instability (NBTI) effect.
Therefore, the NBTI effect should also be considered for the serious degradation of the threshold-voltage in poly-Si. The schematic NBTI mechanism for poly-Si was shown in Fig.4-1-11[4.5].
4-1-3.Capacitance measurement with variable frequency
---determination of the degradation mechanism and regions.
Because the dominant degradation mechanism could not be distinguished from the I-V transfer characteristics, capacitance-voltage (C-V) characteristics were measured. The variation in the C-V results as a function of the frequency allows us to identify whether or not the dominant degradation mechanism is fixed traps or trap states. Fig. 4-1-12(a) (b) (c) show that the connections of gate-to-channel 、
gate-to-drain and gate-to-source capacitances measurement, respectively. Fig. 4-1-13 plots the C-V curves of the TFT before and after stress at a measurement frequency of 50 KHz and 1 MHz. The circle and the inverted triangle symbols present the C-V characteristics of the TFT before and after 1000s AC stress, respectively. The device was stressed with the stress frequency of 1Hz and the duty ratio of 90%. The drain voltage was fixed at -15V, and the pulse of 0V to -15V was applied to the gate electrode. The C-V curves were plotted with normalized value of capacitances, which is the ratio of the measured value to the maximum value of the measured capacitance.
Fig. 4-1-13 shows that the gate-to-channel capacitance versus voltage. The C-V curve in the OFF state (VGS > 0V) in the insert clearly indicate the capacitance increased after stress. The increasing capacitance value was attributed to the increment of parasitic capacitance caused by the generated trapped in the interface [4.6]-[4.7]. In the transition region (-4V<VGS < 0V), it is clearly seen that the shifts of C-V curves are almost the same at 50 KHz or 1MHz. It reveals that the extra positive charges exist in the oxide, because the fixed trap charges are not affected by the applied frequency. As mentioned above all, the degradation of Vth may be originated from the fixed charges in the oxide layer and the interface between the oxide layer and the poly-Si film. To investigate which region the most degradation is in the channel, the gate-to-drain capacitance measurement (Cgd) and the gate-to-source capacitance measurement (Cgs) were employed. Fig. 4-1-14 shows the Cgd curves are shifted in the negative direction and little stretched out as the frequency is increased in the transition region. It indicates that the traps are not fixed traps but grain boundary traps, because the carriers in the grain boundary traps could not catch up with the response to the high frequency. Moreover, the extra increased capacitance in the off state, which indicates the trapped charges mainly occurred in
the interface. Fig. 4-1-15 shows the shifts of Cgs are the same at 50 KHz or 1MHz, which indicates the generated traps are fixed trap charges. Comparing Cgd with Cgs, it is clearly seen that the most degradation exists near the drain regime due to the more thermal energy [4.8].
4-2. The Degradation of N-channel TFT under pulse 4-2-1. Introduction of the degradation characteristics
In order to investigate the reliability of the n-channel TFT, the ac stress was performed in this work. The dynamic stress condition is shown in the Fig. 4-2-1. The rectangular pulse with amplifier of 0V to 15V was applied to the gate electrode and the constant voltage of 15V was applied to the drain. The gate width and length of device are 10um and 4.5um, respectively. The stress frequencies are 1Hz and 10 KHz with duty ratio of 90%. So far, many researches have been reported for the degradation characteristics of the n-channel TFT under dynamic stress [4.9]-[4.12].
The most well-known degradation mechanism is described as following [4.12].
1) As Fig. 4-2-2(a) shown, many electrons were trapped in the channel when the pulse of gate voltage rises from low to high.
2) As Fig. 4-2-2(b) shown, many mobile electrons in the channel when the gate is at the high level.
3) As Fig. 4-2-2(c) shown, the number of mobile electrons decreases accordingly when the gate voltage changes from high to low.
4) As Fig. 4-2-2(d) shown, the trapped electrons start to be emitted, and hot electrons are generated in the region of strong electric field near the drain junction.
Moreover, the hot electrons lead to impact ionization and generate electron-hole pairs. The electrons flow to drain and holes accumulate at the interface between the buffer oxide and the channel poly-Si. When the temperature is high enough in the channel, some of holes are trapped in the buffer oxide [4.13]. As mentioned above, it is helpful for us to analyze the problem in the next section. To demonstrate the degradation mechanisms, two kinds of measurement were used as shown in Fig.
4-2-3. One of them was the forward mode, in which the drain was connected to the positive voltage and the source was grounded; the other was the reverse mode, in which the roles of source and drain were switched.
4-2-2. The effects of low-frequency ac stress
4-2-2. The effects of low-frequency ac stress