The short channel effect of FinFETs has been studied numerically and experimentally by several research groups [6-8]. Pei et al. proposed that in order to suppress SCE, the fin thickness must be less than one third of the channel width [6]. Chau et al. reported that to maintain full substrate depletion, the Si body thickness should be about 1/3 or 2/3 of the gate length in the case of single gate or double gate structures, respectively [7]. In the case of a tri-gate structure, the required Si body thickness becomes equal to the gate length [8]. In fact, the threshold channel length depends on the gate structure and the fin concentration. Fig.3-8 shows the subthreshold swing of the MSB and CN FinFETs as a function of fin thickness with Lg=49 nm and 130 nm. The CN FinFETs shows weak fin thickness dependence, which is quite different from the results in some earlier reports [6, 8], which may be explained by the low fin concentration employed in this work. Here, the top gate alone can fully deplete the channel, so the fin thickness does not clearly affect the SCE apparently. The subthreshold swing of the CN FinFETs is worse than that of the MSB FinFETs in Fig.3-8, which may result from the induced higher interface state density induced by the boron penetration.
For the MSB FinFET, thinner fin thickness results in lower subthreshold swing. However, the extent of improvement differs for MSB and CN FinFETs. Furthermore, the 130 nm MSB FinFETs exhibit better swing than the 49 nm MSB FinFETs at all fin thicknesses. Since the CN FinFETs do not show this phenomenon, it cannot be explained by the gate control capability. We suspect that this unusual phenomenon is related to the S/D silicidation.
Fig.3-9(a) and (b) show the plane-view TEM micrographs of the MSB FinFETs with Wf=49 nm and 200 nm, respectively. The silicided narrow fin shows a bamboo structure and only a single grain exists at the front edge of the S/D region. As the fin thickness becomes larger, the S/D region consists of multiple grains. The multi-grain structure results in a non-uniform front edge of the silicide, which in turn results in non-uniform front edge of the ultra-short SDE, as shown schematically in Fig.3-10. As the channel length is short, a minimal
characteristic. This postulation is also supported by the weak fin thickness dependence of subthrehold swing for the CN FinFETs shown in Fig.3-8 because the CN FinFETs have a smooth S/D junction front edge. For thin fin devices, the CN FinFETs show worse swing than the MSB FinFETs. The high external resistance of the un-silicided S/D of the CN FinFETs could explain this phenomenon.
Fig.3-11 shows the DIBL of the MSB and CN FinFETs as a function of fin thickness, indicating a trend similar to the swing. It can be observed that with suitable combination of channel length and fin thickness, MSB FinFETs can be achieved with an excellent performance of nearly ideal subthreshold swing of 60.4 mV/decade and DIBL of 39 mV/V.
3-3 Conclusions
This chapter demonstrates a novel high performance MSB FinFETs with several unique features such as fully silicided S/D, ultra-short SDE, defect free S/D junction, and low temperature processing. A two-step Ni-salicide process is developed to completely convert the Si layer at the S/D region to silicide with controlled lateral silicidation. By inserting an ultra-short SDE using the ITS technique, the Schottky barrier is modified so that the barrier width is suppressed at the on-state and is increased at the off-state. In addition, the triple gate wrapping around the fin also effectively diminished the Schottky barrier by the gate-fringing effect. With a 4 nm thick gate oxide, the Ion/Ioff current ratio over 109 is achieved, and the room temperature subthreshold swings of 25 nm and 49 nm MSB FinFETs are as low as 83 and 60.4 mV/decade, respectively. These values are close to the theoretical limitations. The Ion
of the 25nm MSB FinFET at |Vd| = |Vg-Vth| = 1 V is higher than 108 µA/µm or 325 µA/µm, depending on the definition of channel width. The Ion of 108 µA/µm is lower than the conventional devices. However, if we consider the actual deriving capability of devices with the same layout width, the Ion of the MSB FinFET, 325µA/µm, will be compatible with that of conventional planar MOSFETs.
Activation energy analysis indicates that the SDE effectively modifies the Schottky barrier, resulting in excellent electrical characteristics. The same activation energy of the low thermal budget MSB FinFETs and high thermal budget CN FinFETs confirms that the MSB junction is very close to the pn junction and the low temperature process of 600°C is sufficient to drive dopants out of silicide. Since the leakage current of drain junction at the off-state is dominated by the surface generation current due to the surface states at the gate oxide/Si and buried oxide/Si interface, it is thus proposed that to further reduce the Ioff of
MSB devices, the interface quality of gate oxide and buried oxide must be improved.
Structural analysis shows that as the fin width becomes larger than the silicide grain size, the multi-grain structure results in a rough front edge of the MSB junction, which in turn degrades the short channel device performance. This result indicates that the MSB process is suitable for FinFETs.
Beyond the 65 nm technology node, it is predicted that the metal gate and high k gate dielectric must be employed to improve the device characteristics continuously. Furthermore, thermal stability between metal gate and high k dielectric is a critical issue because the conventional S/D process requires a high temperature annealing of at least 900°C. Since the MSB process temperature is around 600°C, the thermal stability issue is relaxed and the interfacial layer formation at high k dielectric and Si interface is also reduced. Furthermore, the low thermal budget produced by the ultra-short SDE helps device scale-down. It can thus be considered that the MSB FinFET is a very promising nano device.
References
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Fig.3-1. Output Characteristics of (a) the MSB FinFET and (b) the SB FinFET with Lg = 25 nm, Wf = 40 nm and TSi = 40 nm.
Fig.3-2. Transfer characteristics of the MSB FinFET with Lg = 25 nm, Wf = 40 nm and TSi = 40 nm.
Fig.3-3. Transfer characteristics of the MSB, SB and CN FinFETs with Lg= 49 nm, Wf= 60 nm, and TSi= 40 nm.
Fig.3-4. Schematic band diagrams of (a) MSB FinFET and (b) SB FinFET during the on-state.
Fig.3-5. Schematic band diagrams of (a) MSB FinFET and (b) SB FinFET during the off-state.
Fig.3-6. Transfer characteristics of the MSB FinFET with Lg = 65 nm Wf = 60 nm, and TSi = 40 nm measured at temperatures from 100 K to 500 K.
Fig.3-7. Arrhenius plots of Ioff at Vgs-Vth = 0.75V and Vds = -1V of the MSB and CN FinFETs with Lg = 65 nm Wf = 60 nm, and TSi = 40 nm.
Fig.3-8. Substhreshold swing of MSB and CN FinFETs with different fin thicknesses as Lg
= 130 nm and 49 nm.
Fig.3-9. Plane view TEM micrographs of the MSB FinFETs with (a) Wf = 49 nm and (b) Wf
= 200 nm.
Fig.3-10. Schematic drawing of the grain structure at the S/D region and the SDE profile of the MSB FinFETs with (a) Wf = 49 nm and (b) Wf = 200 nm.
Fig.3-11. Drain-induced-barrier-lowering of MSB and CN FinFETs with different fin thicknesses (Wf) as Lg = 130 nm and 49 nm.