The development and characterization of MG poly-Si NW SONOS have been studied in this thesis. For the purpose of further improving device performance, some valuable studies for the future work are suggested as follows:
For GAA NW devices the NW’s cross-sectional shape plays a key role. The round-shape is most preferred, while other shapes may suffer from the existence of sharp corners and/or irregular shape which may result in non-uniform field distribution [43]. In this work we’ve found the formed NWs have a shape close to circle, but details about the results are still not clear. Further effort is needed to understand the factors that determine the NW shape.
Next, the O/N/O stack composition and thickness should be optimized to further reduce the operation voltage and/or to increase the P/E speed. In addition to improving the quality of TEOS oxide, replacement with another high-k dielectric is also viable.
Regarding the nitride storage layer, nitride profile engineering in the layer is also a viable approach.
In this study, we have demonstrated many important and interesting results about NW SONOS characteristics. The experimental results show decent electrical characteristics and acceptable memory window with the GAA structure. Nevertheless, it is a pity that we don’t have a complete model to explain the characteristics of the NW SONOS devices. Therefore, performing more simulation work to justify our findings is another urgent work in the future.
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Fig. 2-1 (a)Top-view of the NW device, and cross-sectional view (along Line AB in (a)) of NW SONOS-devices at different steps: (b) Bottom Nitride, TEOS and Nitride formed on Si-substrate capped with a buried oxide. (c) Nitride and TEOS patterned by anisotropic reactive plasma etching. (d) Recessed cavities formed by DHF wet etching. (e) a-Si deposition and annealing, and S/D implant. (f-1) Si removal with anisotropic dry etching.
(f-2) Nitride removal with hot H3PO4 and TEOS removed by DHF. (f-3) Bottom Nitride removal with hot H3PO4. (g-1 to g-3) ONO stacked layer and poly gate deposition.
20nm
Fig. 2-2 Cross-sectional TEM picture of an NW SONOS-device with omega-gate along Line AB of the top layout.
O O
Nanowire
NFig. 2-3 Cross-sectional TEM picture of NW SONOS-device with gate-all-around (GAA) along Line AB of the top layout with channel length of 1μm.
Nanowires
20nm
O ON
Fig. 2-4 Cross-sectional TEM picture of NW-SONOS device with side-gate (SG) along Line AB of the top layout.
Fig. 2-5 Channel Hot Electron Injection (CHEI). Channel hot electrons (CHEs) are produced by the strong lateral electrical field in the pinch-off region, and lead to the generation of extra electron-hole pairs. Portions of hot electrons may inject into the gate dielectric and get trapped in the storage nitride layer.
Fig. 2-6 (a)Energy band diagram of SONOS structure in flat-band condition.
(b)Fowler-Nordheim tunneling occurs when Eox is higher than C
OX
V t Δ .
(c)Direct tunneling occurs when oxide is thin enough and Eox is lower than C
OX
V t Δ .