The ADC converts the continuous analog signal to discrete digital codes for digital signal processing (DSP) in the next stage. Typically, the ADC divides the input analog signal into several sub-ranges, and converts to digital number proportional to the magnitude of the input analog signal during the process of conversion. ADCs are characterized by some different ways to indicate the performance, including resolution, SNR, SFDR, SNDR, dynamic range, DNL, and INL. Actually, the ADC has some non-ideal effects which cause performance to degrade.
2.2.1 Resolution
Resolution indicates the number of discrete levels it can produce over the range of analog value. It describes the quantization accuracy of the ADC, which is also named as effective number of bits (ENOB). In other words, the higher resolution ADC means the more sub-ranges that input range is divided. In general cases, resolution is defined as the base 2 logarithm of sub-ranges and always affected by
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noise and nonlinearity in circuits.
2.2.2 Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is defined as the power ratio of the signal to background noise at the ADC output. The ideal transfer characteristic curve of ADC is shown in figure 2.1(a). Figure 2.1(b) shows the quantization error which is the difference between actual analog value and quantized digital value. It defined as the difference between the dash line and the output signal in figure 2.1(a). The quantization error range is between +1
2Δ and –1 2Δ.
Analog Input Digital
Output
Analog Input Quantization
Error
Δ
+1/2Δ
-1/2Δ
(a) (b)
Figure 2.1 (a) Transfer characteristic curve (b) Quantization error
q(k) is the quantization noise due to quantization process. As figure 2.2(a) shows, quantizer can be model as input signal added by quantization noise. The symbol Δ presents the value of 1LSB expressed as equation (2.1). AFS is full scale range of signal. N is the number of bits. By assumption, the quantization noise, q(k),
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is a uniformly distributed random variable between +1
2Δ and –1
2Δ. In figure 2.2(b), it shows that the probability density function, pdf(q), is a constant value between +1
2Δ and –1
2Δ and is independent of the sampling frequency fS and input signal. The probability density function of the quantization error is expressed as equation (2.2).
2
(b) The probability density function of the quantization error
1,
Hence, the quantization noise power is
1 2 Then, the SNR can be derived
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When the signal amplitude VSwing is equal to 2 VFS
, the maximum value of SNR is expressed as equation (2.6).
max 6.02 1.76( )
SNR N dB (2.6) The equation (2.6) shows the relation between SNR and the number of bit. As N increases by one, the SNR specification increases by 6dB. For example, SNR requires at least 62dB for 10 bit ADC.
2.2.3 Spurious Free Dynamic Range (SFDR) and Signal-to-Noise and Distortion Ratio (SNDR)
When a single frequency sinusoidal signal is applied to an ADC input, the ADC output usually contains a signal component at the input frequency. Due to distortion, it also contains signal components at harmonics frequency. Otherwise, quantization error is also injected to output during conversion. As the figure 2.3 shows, the output signal consists of three components, input signal, distortion and noise level. The spurious free dynamic range (SFDR) is the ratio of the fundamental signal component to the largest distortion component. The signal-to-noise and distortion ratio (SNDR) is the ratio of the signal power to the total noise and harmonic distortion power.
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0 1 2 3 4 5
-120 -100 -80 -60 -40 -20 0
Amplitude (dB)
Frequency (MHz) Input
signal
SFDR
Distortion
Noise level
Figure 2.3 Frequency domain plot
2.2.4 Dynamic Range
Dynamic range is another performance for ADCs. It is defined as the ratio of the input signal level for maximum SNR to the input signal level for 0dB SNR. It means the range of input signal amplitudes for which useful output can be obtained from whole system. Figure 2.4 illustrates a plot of SNR versus input level. When the signal to noise ratio is 0dB, it means that it is the minimum detectable input signal power. If the noise power is independent of the level of the signal, the dynamic range is equal to the SNR at full scale. However, the noise power increases as the signal level increases in some cases. Therefore, the maximum SNR is less than dynamic range that degraded by the noise and the harmonic distortion.
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Input Power
[dB]
SNR [dB]
Peak SNR
Limited by noise
Limited by harmonic distortion
Dynamic Range
Figure 2.4 SNR versus input power
2.2.5 Non-ideality
The ideal ADC transfer characteristic progresses from low to high in series of uniform steps that approximates a straight line when the ramp signal is inputted the ADC. However, the transfer characteristic has several non-idealities such as offset, gain error, and non-linearity shown on the figure 2.5(a), (b) and (c) respectively.
In figure 2.5(a), the offset means the transfer curve shifts by a constant amount.
And in figure 2.5(b), the transfer curve slope is not equal to ideal, which is named gain error. In figure 2.5(c), the non-linearity describes transfer curve steps are not uniform. These non-idealities may be caused by device mismatching, sampling capacitor mismatching, and insufficient gain of the operational amplifier. Usually, offset and gain error are tolerable in some applications.
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Analog Input Digital
Output
Offset
(a)
Analog Input Digital
Output Gain
Error
(b)
Analog Input Digital
Output
Nonlinearity
(c)
Figure 2.5 (a) Offset (b) Gain error (c) Non-linearity
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2.2.6 Differential Non-Linearity (DNL) and Integral Non-Linearity (INL)
Both Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) are important parameter for linearity. DNL is defined as the difference between a real quantization step and an ideal quantization step. In other words, it is a term describing the deviation between two successive conversional values corresponding to adjacent input values. Figure 2.6(a) illustrates DNL, which can be expressed as equation (2.7).
It cannot be smaller than -1. If DNL is equal to -1, a code is missing.
( j) Sj- (LSB)
DNL D
(2.7) INL is defined as the deviation from the ideal slope of the ADC and the center of the real quantization step. It describes the difference between the actual transfer characteristic and the ideal transfer characteristic. Figure 2.6(b) illustrates INL, which can be expressed as equation (2.8).
( j) Tj (LSB) INL D
(2.8) DNL and INL are both plotted as a function of code, and are usually expressed in terms of least significant bits (LSB) of the input.
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j
Analog Input Digital
Output
Tj
Ideal
(a)
j
Analog Input Digital
Output
Sj
(b)
Figure 2.6 (a) DNL (b) INL
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2.3 ADC Architecture
2.3.1 Flash ADC
Flash ADC is the fastest architecture among all the ADCs. In Figure 2.7, the flash scheme includes a comparator array, a resistor string and an encoder. For N-bit resolution, it needs at least 2N−1 comparators to distinguish the analog input from these 2N−1 quantization levels. Every comparator compares the analog input with the reference voltage usually generated by resistor string which is connected between VREF and -VREF to construct the overall reference voltages. If the analog input is larger than the reference voltage, the output of comparator is “1”. Otherwise, the output of comparator is “0”. Then the thermometer code is converted to N-bit binary code by a logic circuit, which also contains the functions for solving sparkle and metastability issues.
+-- +-- +-- +--
+--1 2N-2 2
2N-1
Vi
N Dout
(2N-1)-to-N Encoder
VREF
-VREF
Figure 2.7 Flash ADC architecture
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The flash ADC is favored for high speed converters since there is only one comparing cycle used. In other words, the number of comparators grows exponentially with the number of bits. On the other hand, increasing the quantity of the comparators enlarges the whole area and the power consumption dramatically.
Additionally, the tolerable offset of the comparator become very small for high resolution application. It is a critical point in the circuit design, so it can be only applied in the low resolution. Thus several architectures are proposed, like subranging ADC and two-step ADC. These architectures are used to achieve higher resolution applications and reduce power consumption.
2.3.2 Pipelined ADC
sub ADC
sub DAC
Vj A Vj+1
Dj
+
−
Vjda
(Dj)
Stage 1 Stage j Stage N
Encoder
Dj DN
D1 Vi
Dout N
Figure 2.8 Pipelined ADC architecture
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The block diagram of the pipelined ADC is shown in the figure 2.8. It consists of N stages, each including a sample-and-hold (SHA) circuit, a sub-ADC, a sub-DAC, subtraction, and a residue amplifier. Within each stage, the input signal from last stage is sampled and held. The SHA circuit takes more accurate data to reduce aperture jitter which happens from the instantaneous value of the analog input. After the SHA circuit, the analog input signal is quantized by a coarse sub-ADC. Then the sub-DAC adopts the appropriate reference voltage subtracted from original input signal to generate the residue signal. The residue signal is amplified and applied to the next stage for finer conversion. After the amplification, the first stage can start sampling a new analog input signal. All stages operate as same as the first stage. Finally, the digital outputs are collected by encoder to generate the final digital output.
2.3.3 Successive-Approximation-Register ADC
The block diagram of successive-approximation-register (SAR) ADC is shown in Figure 2.9(a). An N-bit SAR converters utilizes only one comparator with N-times quantization to complete a full conversion, which is similar to the pipelined ADC. At first, input signal compares with the reference voltage Vda which is the half of the full scale of signal. Then the comparison result is applied to the control logic, and it generates the appropriate Vda in the next sub-range. The quantization sequence is shown in Figure 2.9(b). The ADC repeats the procedure until the LSB is decided. The higher resolution need more quantization cycles. It has been a limitation in high speed operation. In recent years, a new topology of SAR ADC is proposed. Asynchronous technique is used to archive high speed operation.
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+
--DAC
Control Logic N CLK
VREF
Vda
Dout Vi
(a)
Vi
Phase 1
Phase 2
Phase 3
Phase 4
1/2
3/4
5/8
11/16
1 0 1 1
(b)
Figure 2.9 (a) SAR ADC architecture (b) Quantization sequence
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2.3.4 Cyclic ADC
A cyclic ADC operates the same as a single stage pipelined ADC shown in the figure 2.10. When the conversion is finished in the clock cycle, the residue signal is amplified feedbacks to the input. Then the cyclic ADC converses the data again.
Generally speaking, the cyclic ADC can reach the resolution as the pipelined ADC.
The stage conversion time is also the same as the pipelined ADC, but the throughput rate is much less than the pipelined ADC. Even if the sampling rate is less than the pipelined ADC, the cyclic ADC takes advantages in hardware and power consumption because of only one stage is reused repeatedly. Therefore it is used for middle speed applications. In addition, the cost is more expensive in advanced CMOS technologies. Because the cyclic ADC can archive small area, it is advantage to cost down in advanced CMOS technologies in middle speed applications.
A
subADC subDAC
+
−
Dout Vi
Figure 2.10 Cyclic ADC architecture
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