CHAPTER 2 RELATED WORKS
2.4 A S QUARE FIFO
Ebergen presented a square FIFO implemented with GasP circuits [17]. The square FIFO is one of the low-latency and power-efficient FIFOs, and it consists of a two-dimensional array of stages. The route of one data item is schemed by the FSM specification of stages and the input-output behavior is the same as usual FIFOs.
Figure 2.10 illustrates the operation of a square FIFO with 16 stages. It consists of a top
row of stages, some column FIFOs which are simple linear FIFOs, and a bottom row of stages.
The top row sends out the data items to the column FIFOs in a round-robin fashion, and the bottom row also receives the corresponding data items in a round-robin fashion. Because every data item must go through stages of the square FIFO in order, the data items are distributed to their fixed route.
Figure 2.10 : The square FIFO’s data movements
The data items goes through the square FIFO via four possible paths which are drawn by the dotted lines. The first data item goes through the square FIFO in the sequence S1, S2, S3, S4, S8, S12, and S16 stages. The routing path of the second data item is S1, S2, S3, S7, S11, S15, and S16. The routing path of the third data item is S1, S2, S6, S10, S14, S15, and S16. The routing path of the fourth data item is S1, S5, S9, S13, S14, S15, and S16. It needs the round-robin scheme and then repeats the same routing path. Therefore the routing path of fifth data item is the same as the first one and so on.
All data flow paths in figure 2.10 are listed in the table 2.1 where the variable m is an integer and m can be considered as the number of cycles. For example the routing path of the 21th data item is 4m + 1st in the table 2.1.
Table 2.1 : All paths of the square FIFO
The kth data item Through stages from input port to output port
4m + 1st S1ÆS2ÆS3ÆS4ÆS8ÆS12ÆS16
4m + 2nd S1ÆS2ÆS3ÆS7ÆS11ÆS15ÆS16
4m + 3rd S1ÆS2ÆS6ÆS10ÆS14ÆS15ÆS16 4m + 4th S1ÆS5ÆS9ÆS13ÆS14ÆS15ÆS16
The full control circuits of the square FIFO is shown in figure 2.11. The control circuits for data paths dictates data movements by letting the corresponding pass gates transparent. In figure 2.11, the stages 5~12 are simple linear pipeline shown in the above section. The control circuits for the top row are in the stages 1~4, and the bottom ones are in the stages 13~16. Therefore the FSM specification of stage 5~12 are the same as a linear FIFO in figure 2.8. However special FSM specification is needed to describe the top and bottom rows. Because the bottom row is easier to be described than the top row, the bottom row is presented first.
The problem for the bottom row is to determine when a data item can be received from the left-side or up-side. Most solutions involve counting mechanism, but the solution of [17]
is different. Its rule for each stage of the bottom row is shown as follows :
“If the present data item passing through a stage comes from the left-most stage, the next data item for the stage must come from the stage above. Otherwise the next data item comes from the stage to the left. The first data item comes from the stage above. “
The rule of the bottom row can guarantee the order of data items because it totally corresponds the sequence of data items sent out by the top row. The rule of the top row is
similar to the rule of the bottom row, and the problem for the top row is to determine when a data item can be sent to the right-side or down-side. The solution of the top row is also similar to the one of the bottom row. Each stage of the bottom row looks to a special data item moving right, and each stage of the top row looks to a special “bubble” item moving left. The interpretation of a bubble is a movement that involves both a movement of a data item to the right and a movement of a bubble item to the left. So the rule for each stage of the top row is shown as follows :
“If a data item moves into a stage of the top row by means of a swap with a bubble originating from the right-most stage, the next data item move out of the stage must be down; otherwise, the next data move item must be to the right. Initially, each stage of the top row is empty.”
The rules for each stage of the top and bottom rows are explained above. Figure 2.12(a) illustrates the data moves of the top row. To keep track of whether a bubble comes from the right-most stage or not, it uses two types of arrows to distinguish. One is the dotted arrows which keep the track of a bubble coming from the right-most stage, and the other is the solid arrows recording all the other moves. Figure 2.12(b) is similar to figure 2.12(a). It shows the data moves of the bottom row. In order to keep track of whether a data item comes from the left-most stage or not, it also uses two types of arrows to distinguish. One is the dotted arrows which record a data item coming from the left-most stage, and the other is the solid arrows recording all the other moves.
Figure 2.11 : The control circuits of the square FIFO
Figure 2.12 : (a) The stages of the top row (b) The stages of the bottom row
The rules for each stage of the top and bottom rows are explained clearly, and now we can give the FSM specification for the top and bottom rows. The FSM specification of stage 1 is shown as follows:
Let us translate FSM specification into GasP modules. Figure 2.13(a) shows the stage 1 with data moves, and then we use the FSM specification to draw the processing graph in figure 2.13(b). Finally, we translate the processing graph in figure 2.13(b) into the implementation of GasP modules in figure 2.13(c).
In figure 2.13(a) and (b), the dotted arrows represent the bubbles coming from the right-most stage of the top row, and they use prefix “rr” instead of “r”. Then we translate the FSM specification of stage 1 into figure 2.13(b). The states E0, E1, F0, and F1 are corresponded to the circles in figure 2.13(b). The modules r0, rr0, r1, rr1, and d1 are also corresponded to the lines in figure 2.13(b). Circles and lines connect with one another by the relationships of FSM specification. Finally, we translate the circles in figure 2.13(b) into tri-state wires in figure 2.13(c), and transforming the lines in figure 2.13(b) into the real GasP modules in figure 2.13(c).
Figure 2.13 : Stage 1 (a) Stage with data moves (b) The processing graph for FSM specification (c) The GasP modules of stage 1
The FSM specification of stage 16 is similar to the stage 1, and it is shown as follows:
Stage 16 =
state E0 where
E0 = ( d12 -> F0 ) F0 = ( r16 -> E1 )
El = ( r15 -> F0 | rr15 -> F1 ) F1 = ( rr16 -> E0 )
end
Figure 2.14(a) also shows the stage 16 with data moves, and the processing graph of the stage 16 in figure 2.14(b). Finally, the implementation of GasP modules is in figure 2.14(c).
The dotted arrows in figure 2.14(a) and (b) stand for the data items coming from the left-most stage of the bottom row, and they also use prefix “rr” instead of “r”. Then we
transform the FSM specification of stage 16 into figure 2.14(b). The states E0, E1, F0, and F1 are corresponded to the circles in figure 2.14(b). The modules r0, rr0, r1, rr1, and d1 are also corresponded to the lines in figure 2.14(b). Circles and lines link with one another by the relationships of FSM specification for the stage 16. Finally, we transform the circles in figure 2.14(b) into tri-state wires in figure 2.14(c) and translate the lines in figure 2.14(b) into the real GasP modules in figure 2.14(c).
Figure 2.14 : Stage 16 (a) Stage with data moves (b) The processing graph for FSM specification (c) The GasP modules of stage 16
The stages 2 and 3 of the top row are similar to stage 1, and the stages 14 and 15 of the bottom row are similar to stage 16. The other stages are all simple one-stage linear FIFO.
Since all stages of the square FIFO can be understood, the control circuits of the square FIFO can be implemented as shown in figure 2.11.