This project use Altera’s UP1 board and MAX+PLUS II software.
The UP1 education board is a stand-alone experiment board base on two of Altera’s leading families: MAX 7000 and FlEX 10K. Its simple design when used with MAX+Plus II software, provides a superior platform for learning digital logic using high-level development tools and PLDs.
EPF10K20 Device
THE EPF10K20 device is based on reconfigurable SRAM elements.
The EPF10K20 device is available in a 240-pin RQFP package and has 1,152 Les and six EABs. Each Le consist of a four input LUT( a
programmable flipflop),and dedicated signal paths for carry-and-cascade function. Each EAB provides 2048 bits of memory which can be used to create RAM,ROM, or FIFO function. The EABs can implement logic functions, such as multiplier, microcontroller, state machine, and DSP functions. With 20,000 typical gates, the EPF10K device is ideal for introductory digital design course.
This time my program will be compiled and I need to indicate program’s output signal to FLEX 10K’s pins. After this steps, program will be downloaded into FLEX 10K on UP1 board, then connect
keyboard, monitor we can see the result on screen.
The pins in the program is needed as follows:
FLEX_SW1 Pin Assignments
Switch EPF10K20Pin
D-Sub Connections
Signal D-Sub Connector Pin EPF10k20 Pin
RED 1 236
GREEN 2 237
BLUE 3 238
GND 6,7,8,9,10,11 -
HORIZ_SYNC 13 240
VERT_SYNC 14 239
NO Connect 4,5,9,15 -
Mouse Connections
Mouse Signal Mini-DIN Pin EPF10K20 Pin
MOUSE_CLK 1 30
MOUSE_DATA 3 31
VCC 5 -
GND 2 -
圖一 UP1 board 及其週邊
About VGA :
Each standard VGA monitor has an internal clock, its frequency is 25.175Mhz .The monitor total has 640*480 pixels, row has 480 pixels, column has 640 pixels. Each pixel can display red, green, and blue three kind colors.
圖二 Vga 營幕
VGA timing:
For the VGA monitor to work properly, it must receive data at specific times with specific pulses. Horizontal and vertical
synchronization pulses must occur at specified times to synchronize the monitor while it is receiving color data. Timing waveforms for the color information with respect to the horizontal and vertical synchronization signals.
圖三 VGA Horizontal refresh cycle (0,0)
(640,480) 640 pixels
480 pixels
圖四 VGA Vertical refresh cycle
Following equations explain how to get the time for the monitor to display well.
Time for each pixel : 1/clock frequency = 40ns
Time for each row : ( 40ns * 640 ) + row guild bands = B+C+D+E = 31.77us
Time for screen : 31.77us*480 + guild bands = P+Q+R+S =16.6ms so be careful when coding the VGA code, must bigger or equal than the time required, else will occur unexpected error.
About PS/2 Keyboard:
The Altera UP1 board supports the use of either a mousse or keyboard using the PS/2 connector on the board.
The PS/2 port consists of 6 pins including ground, vdd, keyboard data, and a keyboard clock line. The UP1 board supplies the power to the mouse or keyboard. Two lines are not used. The keyboard data line is pin 31 on the flex chip, and the keyboard clock line is pin 30.
Make and Break Codes
The keyboard scan codes consists of ‘Make’ and ‘Break’ codes. One Make code is sent every time a key is pressed. When a key is released, a break code is sent. For most keys, the break code is a data stream of F0 followed by the make code for the key. Be aware that when typing, it is common to hit the next key before releasing the first key hit.
Using this configuration, the system can tell whether or not the key has been pressed, and if more than one key is being held down, it can also distinguish which key has been released.
When implementing the interface code, it will be necessary to filter the slow keyboard clock to ensure reliable operation with the fast logic inside the FLEX chip. Whenever an electrical pulse is transmitted on a wire, electromagnetic properties of the wire cause the pulse to be
distorted and some portions of the pulse may be reflected from the end of wire. On some PS/2 keyboards there is a reflected pulse on the cable that is strong enough to cause additional clocks to appear on the clock line.
Here is one approach that solves the reflected pulse problem. Feed the PS/2 clock signal into a 8 bit shift register that use the 25Mhz clock.
AND the bits of the shift register together and use the output of the AND gate as the new “filtered” clock. This prevents noise and ringing on the clock line from causing occasional extra clocks during the serial to parallel conversion in the FLEX chip.
The computer system or FLEX chip sends commands to the PS/2 keyboard as follows:
1. System drives the clock line Low for approximately 60us to inhibit any new keyboard data transmissions.
2. System drives the data line Low and then release the clock line to signal that it has data for the keyboard.
3. The keyboard will generate clock signals in order to clock out the remaining serial bits in the command.
4. The system will send its 8-bit command followed by a paritybit and a stop bit.
5. After the stop bit is driven High, the data line is released.
Upon completion of each command byte, the keyboard will send an acknowledge signal, FA, if it received the data successfully. If the system dos not release the data line, the keyboard will continue to generate the clock, and upon completion, it will send a ‘re-send command’ signal, FE or FC, to the system. A parity error or missing stop bit will also generate a re-send command signal.
圖五 System Transmission of a Command to PS/2 Device
Scan code set for the PS/2 Keyboard
PS/2 keyboard are available in several languages with different characters printed on the keys. A two-step process is required to find the scan code. A key number is used to lookup the scan code. Each key sends out a make code when hit and a break code when released. When several keys are hit at the same time, several make codes will be sent before a break code. The keyboard powers up using this scan code as the default.
Commands must be sent to the keyboard to use other scan code sets. The PC sends out an initialization command that forces the keyboard to use the other scan code.
Key# Make The remaining key codes are a function of the shift, control, alt, num-lock
圖六 Scan Codes for PS/2 Keyboard
key No Shift or Num Lock
Shift*
# Make Break Make Break 75 E070 E0F070 E0F012E070 E0F070E012 76 E071 E0F071 E0F012E071 E0F071E012 79 E06B E0F06B E0F012E06B E0F06BE012 80 E06C E0F06C E0F012E06C E0F06CE012 81 E069 E0F069 E0F012E069 E0F069E012 83 E075 E0F075 E0F012E075 E0F075E012 84 E072 E0F072 E0F012E072 E0F072E012 85 E07D E0F07D E0F012E07D E0F07DE012 86 E07A E0F07A E0F012E07A E0F07AE012 89 E074 E0F074 E0F012E074 E0F074E012
Num Lock On 95 E04A E0F04A E0F012E04A E012F04A
Key Scan Code Control, Shift case
# Make Break Make Break 124 E012E07C E0F07CE0F012 E07C E0F07C
Alt case
Make Break 84 F084
圖七 Scan Codes for PS/2 Keyboard