Appendix A The MAPPER System
MAPPER Lithography BV is founded in 2001 by scientists in Delft University of Technology. The MAPPER system uses 13,000 beamlets simultaneously writing patterns on wafer at 5keV. A bundle of electrons emitted from one high current source are guided to massive aperture array to generate 13,000 beamlets. Beamlets are switched on and off by electrostatic blanker array, and passing through the deflecting and focusing lens array at the last stage. To form a scanning field of 26×
10mm2, the beam spots are arranged in a 200×65 array. The deflecting width of an individual beam is 2um. The MAPPER system aims at throughput about 10 300mm wafers per hour in 32nm node and it’s still under developed.[1][2][3]
Figure 5 Schematic of MAPPER system[1]
Appendix B Advantest’s Multi Column Cell (MCC) System
ent, proposed their multiple-colum
Figure 6 Schematic of MCC system[6]
Advantest, one of the leaders of semiconductor test equipm
n electron beam lithography called MCC systems. CC is a tiny column witch only drives one 50keV high energy beam. Unlike other systems focused on the direct write technique, Advantest designed to apply character projection (CP) to their MCC system. CP technique prepares about 200 types of patterns on the CP aperture masks and images the patterns selected onto the wafer through the demagnification projection lenses and deflectors. The alpha-tool has a 4
×4 CC array and focuses on 65nm mask production. Advantest plans to combination of CP technology with variable shaped beam (VSB) and forming a new writing strategy of variable character projection (VCP). The throughput and capability of patterning will be extended by applying VCP technologies.[4][5][6]
Appendix C Canon’s System
hree leaders of lithographic equipment, proposes a 4096 m
Canon, who is one of the t
ultiple e-beam system which drives at 50keV beam energy. Electrons emitted from one thermionic source are split into 4096 beamlets by an aperture array.
Deflectors and blankers are integrated below the apertures. A distinct layer named correction lens array (CLA) is attached, in order to correct field curvature induced from the lens systems. This system can expose a 4×4mm2 field at one time, each beam has a 4um deflecting width. Canon’s system is under development, and the official data of throughput evaluated is 56 200mm wafers per hour, which is unrealistic for mass production.[7]
Figure 7 Schematics of Canon’s System[7]
Appendix D KLA-Tensor’s Reflective Electron Beam Lithography (REBL)
KLA-Tensor is one of the top semiconductor equipment suppliers. They propose a multiple e-b
System
eam system which use digital pattern generator (DPG) to generate the desired pattern. DPG consists of 8,000×500 electron mirrors. A bundle of 50keV electrons passing through the magnetic prism are guided to illuminate the DPG. DSG which consists of array of electrodes can be tuned by changing the driving voltages, and distribution of reflected electrons is modified. Then the modified distribution is demagnified and project to the wafer. Minimum line-width on wafer is about 22.5nm. Throughput of REBL is about 5 300mm wafers per hour.
KLA plans to deliver a beta tool in 2007.[8]
Figure 8 Schematic of REBL System
Appendix E Multibeam
beam proposes their ML2 solution based on the concept of vector shaped m
A new company Multi
ultibeam (VSM). The Multibeam system consist of a monoblock of a 10×1 micro-columns array on 30mm centers. Each micro-column has a thermal field emitter, and scans a stripe of 25×2um2. Electrons emitted hold 20keV energy and are accelerated to 50keV at the final part of the column. Each beamlet is square-shaped and by adjusting the focusing magnification, a variable size of square beam is obtained. Currently, the official data of throughput evaluated is about 5 300nm wafers per hour at 45nm node.[9][10]
beam -trim m ing
Figure 9 Schematic of Multibeam System[10]
Appendix F Lieca’s Projection Maskless Lithography (PML2)
Lieca is one of the leaders of optical equipment supplier and propose a e-beam (APS).
5keV
based projection maskless lithography (PML2) system. In PML2, patterns are formed with a dynamic variable aperture array called aperture plate system
electrons pass through the APS and the patterns generated are 200x demagnified, and accelerated to project onto the wafer at 100keV energy and 25nm spot size. The throughput evaluated is about 5 300mm wafers per hour at 45nm node, and the beta tool is planned for 2008.[11][12]
Figure 10 Schematic of PML2[12]
Appendix G Data Representation
The appropriate choice of data representation is an important issue. The data lled Graphic Data System (GDS or GDSII).
format for transferring 2D graphical design data.
format of original layout data is ca GDSII Stream format is the standard file
It contains a hierarchy of structures, each structure containing elements such included polygons, polylines, and structure references. The hierarchy file can transfer to vector type file. And vector type file can further transfer to pixel file. The data size of the hierarchy is smallest, and the pixel file is biggest. However, the e-beam writers need to receive the pixel file. We should consider these three kinds of representations, hierarchical, vector, and pixel, need to define what kind of data type we choose to use.
1. Pixel type format
Pixel type is most widely used in mask-writer. We roughly calculate the data size in pixel type format.
D
Deevviiccee ssppeecciiffiiccaattiioonnss DiD
irreecctt--wwrriittee s sppeecciiffiiccaattiioonnssMinimum feature 32nm Pixel size 16nm
Edge placement <1nm Pixel depth 6 bits/64 gray
Chip size 10 mm Chip data
Table 13 Direct-write specifications
resents relev pecifications for devices with a 32nm um feature size. To meet these requirements, the corresponding specifications for a direct-write pixel-based lithography system are shown on the right side of Table 13.
The
Table 13 p ant s minim
minimum feature size of 32 nm requires the size of 16 nm pixels.
Sub-nanometer edge placement can be achieved using 6-bit gray pixels.
A 10 mm ×20mm chip can represents 10 20 6 4.68
16 16
mm mm bits
nm× nm× pixel Tbof data per chip. A 300mm wafer containing 350 copies of the chip, results in 1365 Tb of data per layer wafer. Therefore, to expose one layer of an entire wafer in one minute requires a throughput of 4.68
Tb
350 28.8 /60 sec
Tb s
×
onds
. In this data format,decompress by decoder chip.
the compression and decompression element is necessary. Pixel data needs to compress to decrease the data size. As the compressed data transfer to the writers, compressed data needs to
2. Vector type format
Fig. 11 data representation for vector and pixel
V simp
of pixels. We mes smaller
, the proximity effect is a big problem
ector type of data representation is a more efficient way to pixel type. For a le graph as Figure 11, it only needs three polygons to describe, instead of a lot
calculate the data size of vector type data is about ten ti than pixel data for a 32 nm half-pitch ordinary layout file.
In vector type format, we need a data transfer chips in the writers to transfer data from vector format to pixel format. If the polygon of layout data contains more pixels, the efficiency of vector type data is much better. However
for vector type data. As the half pitch gets smaller, the proximity effect will get serious. In this saturation, we need use some correction method to redefine the layout data. The figure of layout will be change and the edge of figure will be distortion. The effect will make the size of vector type format get larger.
3. Hybrid data format
We can combine the advantage of vector type and Pixel type to create a new approach. We can use vector type to describe simple polygon part of layout data, and pix the other part (Figure 12). For a polygon, it needs four param
use el type to describe
eter to define, the position X, Y, width and length (W, L), if W and L are smaller than some given value, it means that is not efficient to describe graph in vector type, then we can use pixel type to present the rest graph. Here we use 57 bits to describe a polygon, if one polygon is containing less than 57/5 = 12 pixels, vector type is not efficient. So if W*L is smaller than 12, vector type is not efficient
anymore. For the graph of layout data after proximity correction, it becomes more complex than the original layout data. In this situation, Hybrid approaches may be a good solution. However, in hybrid format, we also need a data transfer chips in the writers to transfer data from hybrid format to pixel format. The implementation of the hybrid data format needs to be further considered.
Vector-based method
Pixel-based method
Figure 12 Diagram for hybrid data format
Appendix H FPGA-based Data Buffer Board
The field programmable gate array (FPGA) based data buffer for management speed lithography system. The processing and rmous data volumes required to parallel switch the individual
efining the chip patterns. It is a challenge to sets high dem
and data rate is used in design for high transfer of the eno
apertures on the programmable blanker, thus d
ands on the data processing and the whole data path requiring data rates in the gigabit/s and even terabit/s range. The requirements for the data buffer including storage capacity, throughput, incorporation of data re-arrangements and transmission coding, error detection, and appropriate interface solutions. The figure of data buffer architecture for high throughput and data buffer hardware is in Figure 13 and Figure 14.
Figure 13 Data buffer architecture for high throughput[14]
Figure 14 Data buffer hardware (16-layer PCB)[14]