Asynchronous Circuits

Synchronous circuit design is still a mainstream today and it does have many advantages to support it such as complete deign flow and many CAD tools. But as mentioned earlier, with the clock frequency getting higher, the more problems will be faced. So asynchronous circuit

design is getting more and more attractive.

Compared with synchronous circuits, asynchronous circuits are clockless systems.

Instead of a global clock signal, asynchronous circuits use handshake protocols between system components to ensure correct sequencing of events. Asynchronous circuits also have several ways to encode data. Of course, it does have its own advantages and drawbacks.

These will be introduced in the following sections.

1.2.1 Handshake Protocols

Fig. 2 is an illustration of asynchronous systems. It can be seen that the communication between sender and receiver are using handshake protocols i.e. Request and Acknowledge signals. The data is sent out from sender to receiver. There are two main handshake protocols in asynchronous circuits [2]. One is called four-phase protocol and the other is called two-phase protocol.

Fig. 2 Illustration of asynchronous systems

Four-phase protocol is shown in Fig. 3. If the data of sender is ready, sender asserts a request signal. Then receiver gets data and asserts an acknowledge signal as a response. Next, sender deasserts its request signal. Finally, receiver deasserts its acknowledge signal. When both signals return to logic 0, it means that handshaking is complete. So four-phase protocol is also called return-to-zero protocol. Some texts may use the term “level signaling” instead of four-phase protocol.

Fig. 3 Four-phase handshake protocol

Two-phase protocol is shown in Fig. 4. The difference between two-phase and four-phase protocols is the meaning of the signal edges. In four-phase protocol, only the rising edges can be active signals. The falling edges in four-phase protocol just mean reset. But in two-phase protocol, the rising edges and falling edges have no difference. In other words, both can represent active signals. Again, when the data of sender is ready, sender sets its request signal from 0 to 1. Then receiver gets data and also sets its acknowledge signal from 0

to 1 as a response. The end of this action means that handshaking is complete. If subsequent data is ready, sender will set its request signal from 1 to 0 to initiate a new process. Then receiver gets data and also sets its acknowledge signal from 1 to 0 to finish this process. So two-phase protocol is also called non-return-to-zero protocol. Some texts may use the term

“transition signaling” instead of two-phase protocol.

Fig. 4 Two-phase handshake protocol

In general, the systems use two-phase protocol are more efficient and have better performance than the four-phase counterparts. However, using two-phase protocol may lead to more complex circuit theoretically.

1.2.2 Data Encoding Methods

There are several ways to encode data [2]. One is called “bundled-data” as known as

“single-rail” encoding. This method is as same as the data in normal synchronous systems.

Every wire represents a bit of data. Another one is called “dual-rail” encoding. Dual-rail means that each data bit is encoded into two wires which called “d.t” and “d.f”. The encoding method is shown in Table 1. The pattern of {d.t, d.f} represents as following: {1, 0} means a valid data “1”; {0, 1} means a valid data “0”; {0, 0} means an empty token; {1, 1} is not

Fig.5 is a diagram of dual-rail data encoding systems. As Fig. 5 shown, the request signal of sender is encoded into one of two wires. So the communication based on dual-rail data encoding is delay-insensitive i.e. it works correctly regardless of the delays in gates and wires.

Fig. 5 Dual-rail data encoding systems

The using of handshake protocol and data encoding method depends on your design requirements. It can be any combinations of handshake protocols and data encoding methods such as four-phase dual-rail protocol or two-phase bundled-data protocol. Fig. 6 is an example of four-phase dual-rail protocol.

Fig. 6 Four-phase dual-rail protocol

1.2.3 Muller C-Element

Muller C-element is a fundamental component in asynchronous circuits. It is a state-holding element just like an asynchronous set-reset latch. The function of Muller C-element is shown in Table 2. When the inputs are logic 1, the output is logic 1. When the inputs are logic 0, the output is logic 0. Otherwise, the output does not change. Fig. 7 shows the symbol of Muller C-element and the gate level implementation. Fig.8 shows the gate level implementation of Muller C-element with reset.

Table 2 Function of Muller C-element

Input 1 Input 2 Output 0 0 0

0 1 No change

1 0 No change

1 1 1

Fig. 7 Muller C-element and its gate level implementation

Fig. 8 Gate level implementation of Muller C-element with reset

1.2.4 Advantages and Drawbacks

Because of the inherent differences from synchronous circuits, asynchronous circuits have many advantages over synchronous counterparts [2]. The advantages are listed below:

(1) Low power consumption: because of no clock signals, asynchronous circuits eliminate the largest part of power consumption in the whole system – clock distribution networks [1]. Also, because the modules in asynchronous systems are active only when needed, they do not consume any standby power.

(2) Average-case performance: in synchronous circuits, the maximum speed which the system can achieve depends on the slowest component. It is worst-case performance.

Compared with synchronous counterparts, asynchronous circuits have an average-case performance. Without a global clock signal, every component can operate at its own speed. As long as a component finishes its computation, the data

can be send out immediately.

(3) No clock skew problems: again, because of no clock signal, asynchronous circuits do not need to consider clock skew problem as synchronous counterparts will face. With the clock frequency getting higher, it is even harder to handle. GALS systems can reduce clock skew problems.

(4) Better modularity: As different modules operate at different clock frequencies, to integrate these modules into a system is not an easy job. Asynchronous circuits use handshake protocols to communicate between modules, so it is much easier to deal with modularity problems. This is another reason that why we use GALS design approach.

(5) Less electro-magnetic noises: because of no clock distribution networks, asynchronous circuits have less electro-magnetic noises.

Of course, asynchronous circuits do have its own drawbacks. One is few CAD tools to support so that asynchronous circuits are hard to design and are not as popular as synchronous circuits nowadays. Handshake protocols also increase design overheads such as area cost because of additional control signals. In addition, there is no hazard can be tolerated in asynchronous systems, or the whole system will malfunction.