temperature can be effectively dropped to 150 °C or lower, and the bonding pressure can be reduced under 1 MPa as well. The tensile test results also indicate that the bonding strength is increased to 30–50 MPa. With annealing after bonding, the strength can be fur-ther raised about 20%[14].
With outstanding electrical properties, compatible with current IC processes, and lower cost than gold, copper diffusion bonding is still the mainstream for 3D applications, though Au–Au bonding method has the superiority of lower bonding temperature than Cu–Cu bonding.Table 2shows the bonding technology comparison from EVG. The long process time and small throughput are still the issues in Cu–Cu diffusion bonding technology. Considering mass production for 3D IC applications, Cu–Cu bonding with high yield and throughput will be the must requirement and important target in the future.
The 3D integration scheme developed in MIT is shown inFig. 6 [15,16]. Two FEOL active device wafers are stacked in a back-to-face fashion and bonded together by means of Cu–Cu diffusion bonding method. To start with, the front side of the top layer on SOI wafer is attached to a handle wafer. The SOI wafer is then thinned back, created the Cu vias and pads, aligned, and bonded to the bottom device layer. The bonding temperature is 400 °C, fol-lowed by post-bonding annealing step for further inter-diffusion at the Cu–Cu interface to promote grain growth. After the handle wa-fer is released, the 3D structure is complete as shown inFig. 6.
Tezzaron has used Cu–Cu stacked bonding technology to fabri-cate fully functional devices, including a variety of standalone memories, CMOS sensor, 3D FPGA, mixed signal ASIC, and proces-sor/memory stack[17]. The stacking method uses (a) wafer-level, (b) via-first, (c) face-to-face first followed by face-to-back stacked
fashion, and (d) Cu–Cu diffusion bonding. Fig. 7 illustrates this 3D stacked scheme and cross-sectional structure using copper me-tal bonding higher than 300 °C[18]. The total height of the stack with several layers increases only by about 15
l
m per wafer.Therefore, even a stack of many layers can be housed in the normal packaging. After the stack is completed, the substrate of the bot-tom wafer can be thinned and finished with standard wire bonding or flip chip assembly.
4. Eutectic bonding
Eutectic wafer bonding is another option for advanced MEMS packaging and 3D integration. Since the eutectic temperature of two metals is lower than their melting points, the wafer bonding with the binary (or more) metal system under their eutectic point can be achieved at low temperature. A unique feature of eutectic metals is the melting of the solder-like alloys that facilitate surface planarization and provides a tolerance of surface topography and particles. At present, the commonly used materials include Cu–
Sn, Au–Sn, Au–Si, and Sn–Pb. For Cu–Sn case, the bonding temper-ature is 150–250 °C. A post aging process, 250–300 °C for 5 min, is necessary to let the unstable Cu6Sn5IMC completely transfer to the stable Cu3Sn phase. However, the electromigration (EM) intrinsic reliability issue of the Cu–Sn microconnections has to be addressed because of the increased demand for higher interconnect densities and reduced bump size[19]. The eutectic bonding temperatures for Au–Sn and Au–Si are 290 °C and 363 °C, respectively[20]. The temperature for Sn–Pb is 183 °C, which is a mature and low tem-perature electrical bonding method. However, this approach is 484 C.-T. Ko, K.-N. Chen / Microelectronics Reliability 50 (2010) 481–488
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not preferred due to the lead-free tendency for all electronic products.
ASET has developed Cu–Sn connection technique in stacking integration for micro-pitch connection and stacking connection of thin chips[21,22].Fig. 8shows the process flow and finished four layer stacked module developed in ASET. The via-first process is used, followed by thinning process to protrude the TSV stick for Cu–Sn stacked bonding. Here tin is deposited by electroless plating method, and finally forms the Cu3Sn IMC with copper after eutectic bonding. Four layer stacked module on Si interposer is achieved with 20
l
m pitch TSV and 50l
m each chip thickness, as shown inFig. 8.In IZM, the so called ICV-SLID technology[23]is optimized for chip-to-wafer stacking and provides a very high vertical intercon-nect density (>105cm 2) based on inter-chip vias (ICV) between metallization levels of stacked dice. Both the mechanical and ver-tical electrical connections are realized by solid–liquid-inter-diffu-sion (SLID) of thin electroplated and structured copper/tin layers [24]. Fig. 9 shows the 3D integration structure developed with ICV-SLID technology. The thinned chips with tungsten- or cop-per-filled inter-chip vias are connected to the bottom device wafer by the SLID system (Cu, Cu3Sn, Cu). Here the wafer thickness is down to 10
l
m with ICV size 2l
m only. Thermal bonding condi-tions (260–300 °C and 5 bar) are used to compose the stable Cu3Sn alloy. The fully modular concept allows the formation of multiple device stacks.ITRI’s research mainly focuses on the integration of low cost La-ser-drilled Through Silicon Interconnect (LTSI) technology[25–27].
There are four major processes in the LTSI process flowchart, including wafer thinning, direct laser drilling/patterning, insula-tion layer formainsula-tion and PCB compatible via filling/wet etching.
This provides more advantages than other competing technologies not only in the compatibility with low cost silicon-through processes but also in the flexibility to the inter-chips or inter-wa-fers assembly of connecting different components. The feature of this structure is the through-hole copper interconnect with poly-meric material insulation. In addition, Cu–Sn eutectic bonding is studied for chip-to-wafer silicon-through vertical interconnect of
3D stacking packaging. The average value of contact resistance ranges from 0.74 mXto 1.5 mX, and the reliability test also shows good results on the 3D chip stacking structure. Fig. 10 demon-strates the 20-chip stacking performed with LTSI and Cu–Sn bond-ing technologies[28]. The corresponding X-ray image is shown to realize the well 3D interconnection and integration on the stacked chips.
5. Silicon direct bonding
Silicon direct bonding, also as known as fusion bonding, is the spontaneous adhesion of two wafers placed in direct contact. The Si-to-Si and SiO2-to-SiO2wafer bonding are the major targets. This method describes the room temperature bond between wafers with or without dielectric layers, followed by a wet chemical or plasma activation step. The wafer surface needs to be very smooth with small total thickness variation (TTV). In bonding process, two-step technique is performed with room temperature contact fol-lowed by a high temperature anneal, typically, 1000 °C, to let the interface change from hydrogen bonds to strong covalent bonds (Si–O–Si). It offers a high bonding strength in combination with stress free and hermetic sealed bonded structures. However, the high anneal temperature is higher than thermal budgets of some applications, and the method is very sensitive to particle contam-ination. It has been reported that a particle with a diameter of 1
l
m can cause a 1 cm in diameter void when bonding an 8-in wa-fer[29].Fig. 9. The 3D integration platform developed with ICV-SLID technology in IZM Fig. 10. 20-Chips stacking performed with LTSI and Cu–Sn bonding technologies in C.-T. Ko, K.-N. Chen / Microelectronics Reliability 50 (2010) 481–488 485
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One method of IBM 3D integration platforms uses silicon di-rect bonding approach for the permanent wafer bond [30]. As shown inFig. 11, the front side of device SOI wafer is temporary bonded first to a glass handling wafer by organic adhesive. The device SOI wafer is then thinned to an etch-stop layer, the oxide layer (BOX) in SOI wafer, sequentially aligned and bonded to a second pre-processed device Si wafer using wafer bonding with inorganic dielectric layers (SiO2). The wafer bonding process is chemically or plasma activated oxide-to-oxide fusion bonding, which is compatible with BEOL wafers. After the temporary glass handle wafer release, the inter-wafer vias are fabricated using Cu damascene process. The via size is 0.2
l
m only with 2l
m depth around, which means each stacked layer is about 2l
m increase in total thickness, and the via density reaches to a high number of 108cm 2. If required, a third wafer (or more) can be further added to achieve multi-layer 3D structures. Another approach for comparison is the integration where SiO2direct bonding takes place without a handling substrate, which means the bulk lower wafer and SOI upper wafer are fabricated and bonded face-to-face, and then TSVs are formed after backside thinning to the BOX of SOI wafer[31].6. Hybrid bonding
Hybrid bonding is one emerging approach for wafer-level 3D integration[32–36]. It combines metal-to-metal bonding and wa-fer bonding with organic adhesives (ex. BCB) or inorganic dielec-trics (ex. oxide), which can achieve intrinsic metal interconnection with adhesive serving reinforcement of the mechanical stability between stacked ICs. Because the adhesives or dielectrics can simultaneously act the roles of bonding material and underfill, they effectively increase the bonding strength and raise the device reliability. Moreover, because the electrical inter-connect and micro-gap filling can be fabricated at the same time, it simplifies the process flow and avoids the micro-gap filling chal-lenge, and therefore increases the throughput and yield.
IMEC is developing the simultaneous Cu–Cu and compliant dielectric bonding for 3D stacking, named collective hybrid bond-ing[34,36]. It combines fixation of a thin wafer or die by means of dielectric adhesives with the formation of metal interconnects.
Fig. 12shows the illustration of the 3D-SIC (3D-Stacked IC) concept with the hybrid bonding concept by IMEC. The introduction of a tacky polymer as an intermediate glue layer in the direct bonding scheme offers the possibility for die-to-wafer throughput optimi-zation. The method includes pick-and-place of die and then bond-ing operations, as shown inFig. 13. First, the TSV-dies are aligned and placed onto a landing wafer on which the polymer glue layer has been previously processed and patterned. This patterned tacky dielectric weakly bonds the stacked dies and fixes them during fur-ther handling. The operation is performed ideally at low tempera-ture with the pick-and-place process repeated until the full wafer is populated. In second step, the fully populated wafer is moved to a wafer-level bonding tool where pressure and heat are applied to all stacked dies at once. Thus, the dielectric layer reflows and the metallic interconnect bonding is performed for all stacked dies simultaneously. BCB is one of the candidates as the glue material in this approach. After collective hybrid bonding of TSV-dies to a landing wafer, electrical measurements of daisy chains show a comparable and reproducible yield of 80% with working chains up to 1000 TSVs.
Fig. 11. Schematic representation of layer transfer and silicon direct bonding technologies in the IBM 3D integration platform[8].
Fig. 12. Illustration of the 3D-SIC concept in IMEC: dies are separated by a thin dielectric glue layer, and interconnected through silicon Cu vias (TSVs)[34].
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In IBM, a 300 mm wafer-level three-dimensional integration (3DI) process using tungsten TSVs and hybrid Cu/adhesive wafer bonding is demonstrated[33,35]. The process flow for 3DI technol-ogy is shown inFig. 14. The W TSVs have fine pitch (5
l
m), small critical dimension (1.5l
m), and high aspect ratio (17:1). Lower CTE mismatch with surrounding Si and associated thermo-mechanical reliability benefits are included by using W TSV fill.However, because CVD W deposition results in very high stress
film during deposition and is difficult to deposit more than about 1
l
m thickness, design of W vias is suggested as less than 2l
m diameter with tight pitch. After W TSV formation, oxide insulation and Cu studs are formed on the top wafer. The bottom wafer uti-lizes Cu pads with recessed polymer adhesive openings. The wafers are then aligned and bonded in vacuum using hybrid Cu/adhesive bonding approach, also called transfer-join (TJ) method. After bonding, the top wafer is thinned to 20l
m in feature, and backside Cu metallization is patterned. The image of a completed 300 mm 3DI wafer after depositing and patterning of the backside Cu BEOL metallization is shown inFig. 15. The electrical and physical prop-erties of the TSVs and bonded interconnects are presented. RLC val-ues show that both the power delivery and high-speed signaling requirements are satisfied for high-performance 3D systems.7. Conclusions
This review paper summarizes wafer-level bonding technolo-gies for 3D integration. Corresponding 3D integration technolotechnolo-gies and platforms developed in world-wide companies or institutes are also introduced. Advantages and disadvantages of each bond-ing technology are discussed. Adhesive bondbond-ing has better particle contamination tolerance on wafer surface. However, this technol-ogy has potential contamination concerns on devices and fabrica-tion tools. Metal diffusion and eutectic bonding provides direct interconnection, but un-bonded area with air gap may result in reliability issues. Silicon direct bonding provides high via density and better alignment, but the requirements of clean surface and bonding environment are very significant. Hybrid bonding, com-bines metal and adhesive/oxide bonding, can simultaneously achieve interconnect with adhesive serving reinforcement of the mechanical stability between stacked ICs. With high yield and Fig. 14. Schematic diagram of 3D process flow developed in IBM[35].
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reliability superiority, hybrid bonding has become an emerging ap-proach for 3D integration.
Acknowledgements
This research is supported by the Republic of China National Science Grant Council Grant No. NSC 98-2218-E-009-013-MY2.
The authors acknowledge support from National Chiao Tung University.
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