We have developed an optimized deposition condition for Sol-Gel Zr0.03Zn0.97O semiconductor film and succeeded to fabricate a Zr0.03Zn0.97O based - transparent thin film transistor with bottom-gate structure . The optimal conditions for depositing the Zr0.03Zn0.97O film by Spin Coater at room temperature is baking 300°C on the Hotplate . With the development of wet etchants , Zr0.03Zn0.97O active regions can be patterned exactly and completing TFT device fabrication. Followed by the implementation of thermal annealing at different temperature , the mechanism and the effect of thermal treatment on Zr0.03Zn0.97O films also were studied in detail. High temperature annealing process seems to cause the high carrier concentration , and increase the conductivity dramatically. The most suitable deposition condition for Zr0.03Zn0.97O films with sol-gel system have been successfully established by annealing ZnO at 425℃ and with 30 sccm oxygen flow at 0.3 torr. Then , the experiment of thickness on Zr0.03Zn0.97O films at spin-coating procedures , the mechanism and the effect of thickness on Zr0.03Zn0.97O films also were studied particularly . It confirms the high carrier concentration with thickness because of the size of grain. It has be demonstrated that we can obtain the best device characteristic when thickness of the film is between 1100A ～ 1200A . Since the improved mobility is suspected to be related to the decreased roughness of the
interface between the semiconducting layer and the gate insulator . This phenomenon may be attributed to rough channel/dielectric interface with SiNx dielectric layer , thus , we describe the introduction of a HfOx capping layer onto the SiNx films. In other words , in order to get a good device , we replace SiNx with HfOx / SiNx as dielectric layer.
For large area flat-panel display fabrication , the chemical solution deposition process provides a more efficient way for depositing device components than vacuum techniques. In conclusion , We also successfully demonstrated Zr0.03Zn0.97O based - TFT on glass substrate with low annealing temperature.
In the future, Zr0.03Zn0.97O -based transparent thin-film transistors ( TTFT ) can be fabricated because of its unique optical and we also can replace Spin-Coating with Ink-Jetting as deposition technique to reduce the process step.
References
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Appl. Phys. Vol. 42, p. L347 (2003)
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[13] Ü. Özgür,_ Ya. I. Alivov, C. Liu, A. Teke,_ M. A. Reshchikov, S. Doðan,_ V. Avrutin, S.-J. Cho, and H. Morkoç_ JOURNAL OF APPLIED PHYSICS 98, 041301 (2005) [14] B J Norris, J Anderson, J F Wager and D A Keszler, J. Phys. D: Appl. Phys. 36 (2003)
L105–L107
Figure 1-1 shows the ID-VG of ZnO and Zr0.03Zn0.97O based –TFTs.
Figure1-2 shows the corresponding peaks of FTIR for Zr0.03Zn0.97O.
Gate Voltage(V)
0 1000 2000 3000 4000 5000
Absorbance
Figure1-3 shows the hexagonal wurtize structure of Zr0.03Zn0.97O.
Figure2-1 shows a device structure of Zr0.03Zn0.97O based –TFTs.
ZrZnO 400~500Å
substrate
ITO
MoW 1000Å SiNx3000Å
1000Å
Bottom Gate Bottom contact
ZrZnO 400~500Å
substrate
ITO
MoW 1000Å SiNx3000Å
1000Å
Bottom Gate Bottom contact
Zinc atom
Oxygen atom
Hexagonal wurtzite
Figure3-1 shows the corresponding peaks of FTIR for ZrO.
Figure3-2 illustrates the FTIR measurement result of varied baking temperature Zr0.03Zn0.97O film on a single crystalline Silicon substrate.
Figure3-3 illustrates the FTIR measurement result of 350°C curing temperature Zr0.03Zn0.97O film on a single crystalline Silicon substrate at varied baking temperature.
Wavenumber
0 1000 2000 3000 4000
Absorbance
0 1000 2000 3000 4000
Absorbance
Figure3-4 illustrates the SEM measurement result of the ZnO thin films curing at 350°C under oxygen environment.
ZnO ZnO
Figure3-5 illustrates the SEM measurement result of the Zr0.03Zn0.97O thin films curing at 350°C under oxygen environment.
Figure3-6 illustrates the SEM measurement result of the Zr0.03Zn0.97O thin films coating with 400~500A.
Figure3-7 illustrates the SEM measurement result of the Zr0.03Zn0.97O thin films coating with 1100~1200A.
Grain size：10~15 nm
400~500A
Grain size： 20~25 nm
1100~1200A
Figure3-8 shows the complicated structure of the Zr0.03Zn0.97O thin films with the increases of thin films thickness and crystallites size.
Figure3-9 illustrates the AFM measurement result of the Zr0.03Zn0.97O thin films baking at 250°C under oxygen environment.
Rms= 1.539 (nm)
Figure3-10 illustrates the AFM measurement result of the Zr0.03Zn0.97O thin films baking at 300°C under oxygen environment.
Rms= 1.564 (nm)
Figure3-11 illustrates the AFM measurement result of the Zr0.03Zn0.97O thin films baking at 350°C under oxygen environment.
Rms= 3.499 (nm)
Figure3-12 illustrates the AFM measurement result of the Interface contact layer with
SiNx dielectric.
Rms= 15.056 (nm)
Figure3-13 illustrates the AFM measurement result of the Interface contact layer with HfOx / SiNx dielectric.
Rms= 4.441 (nm)
Figure3-14 illustrates the XRD measurement result of varied thickness Zr0.03Zn0.97O films on a single crystalline Silicon substrate.
1400~1500
Figure3-15 illustrates the XPS measurement result of the Zr0.03Zn0.97O thin films curing at 350°C under oxygen environment.
Figure3-16 illustrates the XPS measurement result of the Zr0.03Zn0.97O thin films curing at 425°C under oxygen environment.
524 526 528 530 532 534 536 538
120000
524 526 528 530 532 534 536 538
120000
Figure3-17 illustrates the XPS measurement result of the Zr0.03Zn0.97O thin films curing at 500°C under oxygen environment.
Curing 500°c
524 526 528 530 532 534 536 538
120000 130000 140000 150000 160000 170000 180000 190000
Counts
Binding Energy(eV)
Vo
O 1s
Figure3-18 shows the ID-VD of comparison between baking temperature 250~350°C by hot plate.
Drain voltage(V)
0 10 20 30 40
Drain current(A)
-2.0e-10 0.0 2.0e-10 4.0e-10 6.0e-10 8.0e-10 1.0e-9 1.2e-9 1.4e-9 1.6e-9
Baking250c_Curing350c Baking300c_Curing350c Baking350c_Curing350c
VD-ID(VG=40V)
Figure3-19 show the ID-VG of our Zr0.03Zn0.97O based-TFTs devices with the condition of annealed under 0.3 torr oxygen ambient with different temperature 350 425 500°C for 1 hr.
Figure3-20 shows the ID-VD of our Zr0.03Zn0.97O based-TFTs devices with the condition of annealed under 0.3 torr oxygen ambient with different temperature 350 425 500°C for 1 hr.
Figure 3-21 shows the ID-VG of our devices with the condition of thickness 400~500A , 1100~1200A , 1400~1500A annealed at 350°C under oxygen ambient with for 1 hr.
Figure 3-22 shows the ID-VD of our devices with the condition of thickness
400~500A , 1100~1200A , 1400~1500A annealed at 350°C under oxygen ambient with for 1 hr.
Figure 3-23 shows the ID-VG of our devices with the condition of Interface by different dielectric layer SiNx and HfOx / SiNx .
Figure 3-24 shows the ID-VD of our devices with the condition of Interface by different dielectric layer SiNx and HfOx / SiNx .
Gate voltage(V)
Table 1 shows experimental flow path in my experiment.
Table 2 shows experimental flow chart of sol-gel precursor preparation.
Zn(1-x)ZrxO，x=0.03 Zn(1-x)ZrxO，x=0.03
stirring at 60°C for 30 min Solute： {Zn(CH3COO)2．2H2O}
Table 3 shows experimental flow path of changing baking temperature in my
Experiment Flow of Baking Temperature
350℃_1hr 、Po2=0.6 torr
Table 4 shows experimental flow path of changing curing temperature in my experiment.
ZrZnO
350℃_1hr 、Po2=0.3 torr
425℃_1hr 、Po2=0.3 torr
500℃_1hr 、Po2=0.3 torr Lithography
Baking
Curing Temperature ZrZnO
350℃_1hr 、Po2=0.3 torr
425℃_1hr 、Po2=0.3 torr
500℃_1hr 、Po2=0.3 torr Lithography
Baking
Curing Temperature
Experiment Flow of Curing Temperature
300℃_10min
Table 5 shows experimental flow path of changing film Thickness in my experiment.
Experiment Flow of Film Thickness
350℃_1hr 、Po2=0.6 torr 300℃_10min
Table 6 shows the N&K measurement result of varied thickness Zr0.03Zn0.97O film on a single crystalline Silicon substrate.
0
Table 7 shows experimental flow path of changing interface contact layer in my experiment.
ZrZnO-TFT
SiNx(3000A) HfOx(100A) / SiNx(3000A) Different dielectric
ZrZnO-TFT
SiNx(3000A) HfOx(100A) / SiNx(3000A) Different dielectric
Experiment Flow of Film Interface
Table 8 shows the binding evergy of varied element for the Zr0.03Zn0.97O thin films.
Binding Energy(eV)
Zn-O ≒ 530.15 eV
Vo(Oxygen vacancy) ≒ 531.25 eV
Table 9 shows electronic properties of Zr0.03Zn0.97O based-TFTs with different curing
Table 10 shows electronic properties of Zr0.03Zn0.97O based-TFTs with different thickness of the film.
1*10
4Table 11 shows electronic properties of Zr0.03Zn0.97O based-TFTs with different dielectric layer.
簡 歷 姓 名：蕭 秀 娟 (Shiou-Jiuan Shiau )
性 別：女
出生年月日：民國 71 年 8 月 18 日
住 址：宜蘭市東港路66巷17弄10號之ㄧ 學 歷：
國立中山大學物理學系學士 (90.9-94.6) 國立交通大學光電工程學系顯示科技研究所碩士 (94.9-96.6) 碩士論文題目:
溶膠凝膠法沉積鋯摻雜氧化鋅薄膜電晶體之研究
Study on fundamental properties of ZrZnO-based TFT by Sol-Gel process