In this thesis, the hardware architecture for the texture coding module in the MPEG-4 video encoder is presented. This proposed hardware core can support Simple Profile Level 3, under frame size 352x288 with 30fps for real time video applications. In order to reduce the hardware cost and smaller the processing time, an efficient block engine using the interleaving DCT/ IDCT scheduling is adopted. While this module is integrated into the entire system, it will maintain performance in low cost. Furthermore, the sharing technique for normalizing the AC/DC prediction values and quantizing DCT coefficients is applied to reduce area size further. The ping-pong buffer is designed to buffer motion estimation errors or intra frame data and ensure that all the data in the buffer can be read safely and correctly.
Based on the row-column decomposition technique, the cost-effective VLSI architecture for two-dimensional 2D DCT/ IDCT is achieved. The 2D DCT/IDCT design has a regular structure, simple interconnects and control, and efficient implementation of the inverse transform using the same hardware. The required finite word-length accuracy is analyzed. The DCT/IDCT structure can achieve excellent accuracy and the accuracy conforms to IEEE standard 1180- 1990.
In summary, a cost-effective block engine for MPEG-4 texture coding is presented and achieved. As the architecture can be placed in the regular fashion, it is proper to be implemented with commercial ASIC technologies. The proposed architecture can be applied to the portable multimedia terminal for wireless multimedia services. The future work includes three tasks. First, some improvements in our work to lower power consumption are necessary. These methods include clock gating, skipping input macro block for DCT or IDCT in the encoding loop…etc. Second, more functionality such as error-resilience tools, B-VOP coding will be integrated into the original module to satisfy other video applications. Third,
the decoding functions, such as variable length decoding, will also be designed to integrate into the original architecture to be a MPEG-4 texture codec design.
Reference
[1] MPEG-4 Video Group “Information Technology - Coding of Audio Visual Object-Part2: Visual,” ISO/IEC JTC 1/SC 29/WG 11 M9477, Pattaya, March 2003.
[2] ITU-T Recommendation H.263, “Video coding for low bit rate communication,” ITU-T, 1996
[3] ISO/IEC JTC1 IS 11172, “Coding of Moving Picture and Coding of Continuous Audio for Digital Storage Media up to 1.5 Mbps,” ISO/IEC JTC1, 1992.
[4] ISO/IEC JTC1/SC29/WG Draft CD 13818-2, “General Coding of Moving Pictures and Associated Audio,” ITU-T Recommendation H.262 Committee Draft, 1994.
[5] Fernando Pereira and Touradj Ebrahimi, “The MPEG-4 Book,” Upper Saddle River, NJ : Prentice Hall PTR, c2002.
[6] T. Sikora,“The MPEG-4 Video Standard Verification Model,＂IEEE Trans. on Circuits and Systems for Video Technology, vol.7, No.1, pp.19-31, Feb. 1997.
[7] Atul Puri and Tsuhan Chen, “Multimedia systems, standards, and networks,” Marcel Dekker, New York, c2000.
[8] A.V. Oppenhiem and R.W. Shafer, “Digital Signal Processing,” Prentice Hall, N.J., Englewood Cliffs, 1975.
[9] J. Canaris, “A VLSI Architecture for the Real Time Computation of Discrete Trigonometric Transforms,” Journal of VLSI Signal Processing, vol. 5, pp. 95-104, 1993.
[10] Weiping Li, "A New Algorithm to compute the DCT and its Inverse," IEEE Trans. on Signal Processing, Vol. 39, pp 1305-1313, June 1991.
[11] M. Bousselmi et al., "New parallel architecture of the DCT and its inverse for image compression," IEEE International Conference on Electronics, Circuits and Systems (ICECS 2000), vol. 1, pp. 345-348, Dec. 2000.
[12] A. Madisetti, A. N. Willson Jr., "A 100 MHz 2-D 8x8 DCT/IDCT Processor for HDTV
Applications," IEEE Trans. On Circuits and Systems for Video Technology, vol.5, No.2, pp. 158-165, Apr. 1995.
[13] K. H. cheng et al., “The Design and Implementation of DCT/IDCT Chip with Novel Architecture,” IEEE International Symposium on Circuits and Systems (ISCAS 2000), Geneva Switzerland, vol. 4, pp. 741-744, May 28-31, 2000.
[14] C.W. Hsu, W.M. Chao, Y.C. Chang, and L.G. Chen, “Texture coder design of MPEG-4 video by using interleaving schedule,” in Proc. of 2002 IEEE International Conference on Multimedia and Expo (ICME 2002), Lausanne, Switzerland, August 2002.
[15] Seehyun Kim, Wonyong Sung "Fixed-Point Error Analysis and Word Length Optimization of 8x8 IDCT Architecture,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 8, No. 8, Dec. 1998.
[16] E. E. Swartzlander, Jr., “Truncated multiplication with approximate Rounding,” in Conference Record of the Thirty-third Asilomar Conference on Signals, Circuits and Systems, pp.1480-1483, 1999.
[17] IEEE standard 1180-1990 “IEEE Standard Specifications for the Implementation of 8x8 Inverse Discrete Cosine Transform,” CAS Standards Committee of the IEEE Circuits and Systems Society, Dec. 6, 1990.
[18] K. Suh, S. Park, S. Kim, B. Koo, I. Kim, K. Kim, H. Cho, "An Efficient Architecture of DCTQ Module in MPEG-4 Video Codec," IEEE International Symposium on Circuits and Systems(ISCAS 2002) , vol. 1, pp. I-777 – I-780, 2002.
[19] http://www.xvid.org
Appendix
A-1 . Pin Definitions for MPEG-4 texture coding
Fig. A-1 shows the inputs/outputs of our MPEG-4 texture coding. The descriptions for each pin are depicted in Table A-1.
MPEG-4
Texture Coding Clk
Resetn
Ctrl_texture_en Ctrl_texture_ack ME_MB_X[4:0]
Text_MB_X[4:0]
Text_MB_Y[4:0]
Text_init_L0_frame_ptr_X_table[8:0]
Text_init_L1_frame_ptr_X_table[8:0]
Text_init_L0_frame_ptr_Y_table[16:0]
FrameType Bus_user[2:0]
MB_I_P MC_error[35:0]
DCT_wren DCT_waddress[6:0]
Q_Param[4:0]
Text_init_UV_frame_ptr_Y_table[16:0]
AHB_data_In[31:0]
BistMode
texture_rsp[1:0]
texture_bus_req texture_HWRITE AHB_address_out[31:0]
AHB_data_out[31:0]
MB_Type qcoeff_valid Acdcp_direction Acdcp_flag q_blk_addr[2:0]
q_pix_addr[5:0]
vlc_cbp qcoeff[11:0]
IDCT_cbp IDCT_data_valid IDCT_address_out[6:0]
BistFail[5:0]
IDCT_data_out[35:0]
ErrMap[5:0]
Finish
Figure A-1 MPEG-4 Texture Coding IP.
Table A-1 PIN Definition
Name Direction Width Description
Clk Input 1 Clock signal, positive edge trigger Resetn Input 1 Reset texture coding engine, active LOW Ctrl_texture_en Input 1 Enable Texture coding engine Ctrl_texture_ack Input 1 Acknowledge signal
ME_MB_X Input 5 the MB position in the X-axis for Motion estimation
Text_MB_X Input 5 the MB position in the X-axis for Texture coding
Text_MB_Y Input 5 the MB position in the Y-axis for Texture coding
Text_init_L0_frame _ptr_X_table
Input 9 Offset of the frame pointers for the luminance values in the X-axis
Text_init_L1_frame _ptr_X_table
Input 9 Offset of the frame pointers for the chrominance values in the X-axis
Text_init_L0_frame _ptr_Y_table
Input 17 Offset of the frame pointers for the luminance values in the Y-axis
Text_init_UV_frame _ptr_Y_table
Input 17 Offset of the frame pointers for the chrominance values in the Y-axis
FrameType Input 1 Frame type I or P
Q_param Input 5 Quantization Parameter
bus_user Input 3 AMBA bus user
MB_I_P Input 1 MB type intra or inter
errors in the ping-pong buffer if current frame is the Prediction frame.
DCT_wren Input 1 Enable to write MC errors to ping-pong buffer
DCT_wraddress Input 7 Address for writing MC errors to ping-pong buffer, address [6: 4] indicates the block index and address [3:0] indicates the pixel index.
texture_rsp Output 2 Response to tell the status of texture coding engine(idle, busy, or finish)
texture_bus_req Output 1 Request to use the AMBA bus
AHB_data_in Input 32 Input data from the frame memory through the AMBA bus
texture_HWRITE Output 1 Writing the reconstructed values to the frame memory through the AMBA bus AHB_address_out Output 32 Address of the reconstructed frame AHB_data_out Output 32 Reconstructed frame data for I frame
MB_type Output 1 MB type to VLC module
qcoeff_valid Output 1 Valid signal for quantized coefficients to VLC module
acdcp_direction Output 1 Prediction direction
acdcp_flag Output 1 Prediction flag to decide whether the prediction values are used or not.
q_blk_addr Output 3 Quantization block address bus q_pix_addr Output 6 Quantization pixel address bus
vlc_cbp Output 1 Cbp signal to VLC
qcoeff Output 12 Quantized coefficients to VLC IDCT_cbp Output 1 Cbp to Motion compensation
IDCT_data_valid Output 1 Valid signal to the reconstructed memory in the Prediction frames
IDCT_address_out Output 7 the MC errors Address bus IDCT_data_out Output 36 the reconstructed frame data bus
BistFail Output 6 BIST fail
ErrMap Output 6 Error mapping for BIST mode
Finish Output 1 BIST finish signal
BistMode Input 1 Signal to determine if BIST mode is used or not.
Biography
Publication List
[1] Bing-Fei Wu, Yao-Chun Hung, Yen-Lin Chen, Chao-Jung Chen, Chung-Cheng Chiu, and Chorng-Yann Su ,“A High-Speed Wavelet-Based Video Codec for Video Surveillance System” ,2004 第十三屆全國自動化科技研討會,Taipei, Taiwan , June 17~18
Awards
[1] 交通大學電機與控制工程學系 88 學年度第二學期書卷獎 [2] 第五屆 TIC 100 創業競賽 冬令營 冠軍
[3] 第五屆 TIC 100 創業競賽 總決賽 銀質獎
[4] 教育部九十二學年度大專院校通訊科技競賽研究所組入圍
[5] 第一屆機動車輛創新設計獎(智慧電子化機能創新設計組) 銀質獎 Yao-Chun Hung was born in changhua, Taiwan, R.O.C., on
March 25, 1981. He received the B.S and M.S degrees from the Department of Electrical and Control Engineering, National Chiao Tung University, Taiwan, in 2003 and 2005 separately.
His research interests include video coding algorithms and VLSI architecture for image and video processing.