CONCLUSIONS AND FUTURE WORK

In this thesis, the design methodologies and implementations of key CMOS RFICs including wideband down conversion mixers, a frequency synthesizer, an active inductor based PTAT VCO, and a divide-by-3 SDFD for UWB communication systems are proposed.

Firstly, a wideband mixer using LC folded cascode mixer topology and a modified feedforward compensated differential transconductor in TSMC 0.18-m CMOS technology is presented in the first section of chapter 2. The LC folded cascode method is used to get more voltage headroom, and the feedforward compensated differential transconductor is adopted to achieve broadband impedance matching and lower the overall distortion. The linearity is enhanced by a harmonic distortion canceling technique derived from the harmonic balance analysis. The finished mixer core occupies an area of only 0.7  0.58 mm² with a consumed power of 14.4 mW under 1.8 V supply voltage. For the second section, a wideband down conversion mixer with active balun is proposed. The cascode CG and CS active balun structure exhibits a broadband performance, which provides balance signals for mixer core from single input. The finished mixer core and active baluns possess good linearity, wide bandwidth, and occupy an area of only 0.85  0.57 mm² with a consumed power of 25.7 mW under 1.8 V supply voltage, which is suitable for application in various wireless communication systems.

Secondly, a frequency synthesizer with the SDFD for UWB communication system is proposed and designed. The synthesizer consists of: 1) two PLLs for frequency generation; 2) a divide-by-7 SDFD to generate several frequencies; and 3)

wideband SSB with capacitor switches. The proposed SDFD circuit is introduced to divide the frequency by seven and co-designed with the PLL. As can be seen from the simulation results, the SDFD has the ability to generate several different frequencies to mix for the 14 output bands. The designed CMOS synthesizer has full-band output with 7.6 dBm output power and 111 mW DC power consumption. The proposed synthesizer structure provides a solution to the low-power and high-performance LO.

Therefore, the proposed synthesizer is a favorable choice for use in UWB applications.

Thirdly, an LC-tank VCO with temperature compensation active inductors in TSMC 0.18-m CMOS technology is presented. The frequency variation is less than 1% when the temperature varies from 20⁰C to 60⁰C, which is a great improvement of the oscillating frequency shift for active inductor-based circuits. The measured phase noise is 91 dBc/Hz at 1 MHz offset at 2.4 GHz. The VCO occupies an active area of only 190  195 m² and exhibits a 48% tuning range with a consumed power of 19.3 mW under 1.8 V supply voltage.

Finally, a divide-by-3 SDFD with active balun is presented using the current-reused technique. The presented SDFD is fabricated using the TSMC 0.18-m CMOS process and the die area is 1.1  0.8 mm². Current-reused technique has advantages of less DC power consumption and compact circuitry. This technique is realized by taking the LO switching stage of Gilbert cell mixer as the current sources of static frequency divider. The measurement results presented a DC power consumption of 12 mW with a locking range form 21.48 to 22.56 GHz.

In summary, the CMOS RFICs can be operated with good performance in the UWB systems. Nowadays it is evident that the need for high data rate electronic applications is growing. To meet the demand for high data rate, the applications of UWB system, therefore, will be a better solution.

Future research will be focused on the integration of other RF components to form all-CMOS UWB systems. The active inductor will be applied widely in the future design because the die area is directly related to the cost when the circuits are implemented. Lowering the supply voltage less than 1.2 V will be able to decrease the total power consumption, which gets more flexibility for the electronic application.

The aim of future research is to develop low-cost, high-performance, and high-frequency transceiver front-ends.

APPENDIX

Abbreviation Full name

ADS Agilent Advanced Design System

AI Active Inductor

CGCS Common-Gate Cascaded with Common-Source

CML Common-Mode Logic

CP Charge Pump

DSB Double-Sideband

FCC Federal Communications Commission GPRS General Packet Radio Service

GSM Global System for Mobile

HDMI High-Definition Multimedia Interface HDTV High-Definition Television

IIP2 Second-order Input Intercept Point IIP3 Third-order Input Intercept Point ILFD Injection Locked Frequency Divider IMD3 Third-Order Intermodulation Distortion IP1dB Input 1-dB Compression Point

LF Loop Filter

LO Local Oscillator

MB-OFDM Multi-Band Orthogonal Frequency Division Multiplexing MIM Metal-Insulator-Metal

MMIC Monolithic Microwave Integrated Circuit

NTAT Normal Inversely Proportional to Absolute Temperature PCS Personal Communication System

PLL Phase Locked Loop

PTAT Proportional To Absolute Temperature PVT Process-Voltage-Temperature

RFICs Radio Frequency Integrated Circuits

SCL Source-Couple Logic

SDFD Semi-Dynamic Frequency Divider

SSB Single-Side Band

TSPC True Single Phase Clocking

UWB Ultra-WideBand

VCO Voltage-Controlled Oscillator

W-CDMA Wideband Code Division Multiple Access WLAN Wireless Local Area Network

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