Case Study

In this section, we use apex2 benchmark to observe the effective of four flows for placement and routing in experiment II as various number of layers. The number of layers is 1~8. The logic utilization is set to 75%.

Figure 45 shows the temperature profile at layer 1 of 4-layer design. It can be observed that our TherWare has the smoothest temperature profile significantly.

Figure 45. Temperature profile at layer 1 of 4-layer design

The maximum temperature is increased as number of layers increased in all flows as shown in Figure 46. Observably, our TherWare always has the lowest maximum temperature, and it is about 70℃ decreased at a 8-layer design. Similarly, as shown in Figure 47, the temperature deviation grows as number of layers increases in all flows and our TherWare has the lowest deviation also.

Figure 48 shows the delay at 1~8-layer design. The delay decreases as number of layers increases and becomes saturated, mainly because the benefit on shortening global interconnects for 3D designs.

To combine the tradeoff between temperature optimization and impact on timing, our TherWare framework obtains the most benefit to the temperature behavior with

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less impact on critical delay, which is especially obvious in a 4-layer design.

Figure 46. Maximum temperature at 1~8-layer design.

Figure 47. Temperature deviation at 1~8-layer design.

Figure 48. Delay at 1~8-layer design.

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Chapter 6 Conclusion

In thesis, we first develop a set of fine-grained thermal resistive models with different granularities for 3D FPGAs, named FG-8, FG-4 and FG-2, respectively.

Regarding the finest granularity model – FG-8 as a baseline, the FG-4 is not only accurate but also efficient. For FG-4, the root mean square error is less than 2.5%, and the maximum absolute difference is less than 3.9%. Compared with FG-8, FG-4 also obtains 99.8% correlation and achieves 7.3 times speedup in runtime.

Meanwhile, we also propose a thermal-aware backend framework for 3D FPGAs, named TherWare. Three guidelines are integrated in TherWare placement stage: i) power uniformity – keeping power uniformity between several tiles with placed CLB;

ii) heat dissipativity – letting the potentially hotter tiles can dissipate heat easily; iii) interconnect power – preventing increasing the interconnect power excessively. Our router allows non-timing-critical nets choosing longer paths with lower power consumption, and such an idea will help distribute power more uniform in 3D FPGA designs.

Table 5. Improvements of TherWare vs. different baseline.

The experimental results are summarized in Table 5. TherWare outperforms all related works on temperature, and it has only few overheads in delay and runtime. We conclude that TherWare is the most effective thermal-aware placement and routing for 3D FPGAs up to now.

Baseline Maximum temperature

Temperature deviation

Maximum temperature

gradient

Total power

Delay overhead

Runtime overhead

TPR 25.8% 41.6% 24.7% 7.6% 2.0% 4.2%

3D

MEANDER 16.6% 31.9% 13.3% -7.9% 0.8% 14.0%

Z-tile-P +

TherWare-R 13.1% 26.9% 11.8% 3.7% 0.5% -0.3%

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