Chapter 5 Chip Implementation
5.1 Chip Specification
Table 5.1 H.264/AVC main profile decoder specification for motion compensation
Table 5.1 lists the specification of our bandwidth-efficient motion compensation architecture for H.264 HDTV decoder. After synthesis on Cadence RTL complier using UMC 0.13 um COMS technology, total gate count is 557730 (including embedded SRAM) and the gate count of each component is listed for video decoder in table 5.2. The Die size of H.264
decoder is 3100 mm x 3100mm. Table 5.3 lists on/off chip memory used on each module in our design. The chip photo of H.264 decoder is illustrated as Figure 5.1. The average power consumption of system is 50mW approximately. Furthermore, about synthesis results of our proposed motion compensation and memory controller, the power consumption of motion compensation is 9.53mW and the power consumption of memory controller is 3.9mW at 100MHz, the gate count is 83515 and 8584 for motion compensation and memory controller respectively.
Table 5.2 Synthesis results of H.264/AVC’s main profile decoder including SRAM
Table 5.3 On/Off-Chip memory size for different module in H.264 main profile decoder
CAVLC
Figure 5.1 CHIP photo for H.264/AVC main profile decoder
Chapter 6
Conclusion
In this thesis, we present a bandwidth-efficient motion compensation memory controller organization for H.264 HDTV decoder and support 1080HD 30fps@L4 high-quality format.
The proposed motion compensation engine realizes all advanced features including MV generators with direct modes, combined luma/chroma interpolator, and weighted prediction of H.264/AVC main profile. Concerning the design of interpolator, 4-parallel separate 1-D architecture gives the most space on high throughput video decoder compared with other architectures proposed. An Extend-2D column major approach is presented, and the proposed data reuse technique for fraction motion compensation introduces content buffer, content-swap operation and register-file shifting attached on our interpolator design. This design improves 50%-60% bandwidth with B-slices under external data BUS. Additionally, a combined luma/chroma interpolator is proposed in order to save area, which achieves approximately 44% of cost reduction. Altogether, memory usage and bandwidth are optimized by our proposed design.
Besides, the decoder system bottleneck resulted from the performance limitation of the off-chip SDRAM subsystem leads system designers to put more efforts on SDRAM efficiency.
In conventional SDRAM controller designs, though different requirements for SDRAM service of the heterogeneous system components are often considered, high bandwidth utilization can be achieved for special applications such as high definition TV. For this reason, the proposed memory controller can reduce bandwidth over external BUS using memory
scheduling and improve data access hit rate using data arrangement. For reducing bus utilization, the memory controller architecture is proposed and related approaches are employed as well. This design target of interpolator and frame memory access controller is to reduce external memory access and improve throughput of the entire video decoder. The SDRAM memory access controller appended to video decoder is presented to overcome the tremendous transfer of pixel data to/from external frame memories. To achieve efficient memory access scheduling, we discuss not only memory scheduling but also data arrangement within SDRAM. The proposed data arrangement in our scheduling scheme can minimize the miss ratio (at the same bank) that contributes the maximum latency among all scheduling cases. We create system level hardware-like C++ model and use data utilization to analyze the system performance. Compared to unscheduled situation, the experimental result shows that the access latency can be reduced by 50 % ~ 90 % and bandwidth utilization can be improved up to 90%. In the meanwhile, the throughput of the overall video decoder improves about 50 % ~ 60 % after combining extended RSO method and memory scheduling.
Besides, the gate count of motion compensation and memory controller is 83515 and 8584 respectively in synthesis results. The average power consumption of motion compensation and memory controller is 9.45mW and 3.9mW approximately at 100MHz.
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作 者 簡 歷
姓 名 ： 侯康正
出生地 ： 台灣省台北市
出生日期： 1979. 12. 05
學歷： 1985. 9 ~ 1991. 6 台北縣竹圍國民小學
1991. 9 ~ 1994. 6 台北縣立淡水國民中學
1994. 9 ~ 1999. 6 北台科學技術學院 電子工程科
1999. 9 ~ 2001. 6 國立高雄應用科技大學 電子工程系 學士
2004. 9 ~ 2006. 6 國立交通大學 電子研究所 系統組 碩士
得 獎 事 績
1999 春 教育部單晶片微處理器設計 佳作
1999 秋 義隆盃單晶片微控制器設計組 特優
2006 春 九十四學年度大學校院積體電路(IC)設計競賽 第四名
發 表 論 文
Kang-Cheng Hou, Sheng-Zen Wang, Yi-Hong Huang, Tsu-Ming Liu, Chen-Yi Lee, “A Bandwidth-Efficient Motion Compensation Architecture for H.264/AVC HDTV Decoder”, in Proceedings of the 17th VLSI/CAD Symposium, August 2006.
Yi-Hong Huang, Ping-Chang Lin, Kang-Cheng Hou, Yueh-Chi Hung, Tsu-Ming Liu, Chen-Yi Lee,” A High-Throughput SRAM-Based Context Adaptive Binary Arithmetic Decoder (CABAD) for H.264/AVC”, in Proceedings of the 17th VLSI/CAD Symposium, August 2006.
Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, Kang-Cheng Hou, Jiun-Yan Yang and Chen-Yi Lee, “A 125-μW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications”, is accepted by IEEE Journal of Solid-State Circuits.
Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, Kang-Cheng Hou, Jiun-Yan Yang and Chen-Yi Lee, “A 125-μW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications”, ISSCC Dig. of Tech. Papers, pp. 402-403, San Francisco, USA, Feb. 2006.
Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, Kang-Cheng Hou, Jiun-Yan Yang and Chen-Yi Lee, “An 865-μW H.264/AVC Video Decoder for Mobile Applications”, IEEE Asian Solid-State Circuit Conference, 2005. pp. 301-304, HsinChu, Taiwan, Nov. 2005.