We showed that’s strong FLP on both n- and p-type Ge .Next we successful released the effects of pinning both on n and p type Ge by inserting the interfacial layer of GeO2 and Al2O3, and made the high SHB for hole in P-Ge case. The pinning factor of GeO2 case was 0.41 for P-Ge and 0.59 for N-Ge, while in Al2O3 case the pinning factor was 0.347 for P-Ge and 0.495 for N-Ge. According to the pinning factor we calculated of each sample, the effect of de-pinning by using GeO2 was better than one by using Al2O3, because the interfacial layer of GeO2 cannot only reduced MIGS but also passivated the dangling bonds at the interface. [14]
13
Finally, we found out the different behavior of TiO2 as a blocking layer by applying it to different metal contact. The insertion of TiO2 layer at the metal/n-Ge interface could change the I-V characteristic from rectifying into ohmic, which is due to the semiconductor-like characteristics of TiO2.
14
References (Chapter 2)
[1] Chi On Chui, Leonard Kulig, Jean Moran, Wilman Tsai, and Krishna C. Saraswat,
“Germanium n-type shallow junction activation dependences”, Appl. Phys. Lett. vol. 87, p. 091909, 2005.
[2] John M. Larson, and John P. Snyder, “Overview and Status of Metal S/D Schottky-Barrier MOSFET Technology”, IEEE Trans. Elec. Dev., vol53, NO. 5, 2006.
[3] A. Dimoulas, P.Tsipas, A. Sotiropoulos, and E. K. Evangelo, “Fermi-level pinning and charge neutrality level in germanium”, Appl. Phys. Lett. vol. 89, p. 252110, 2006.
[4] Duygu Kuzum, Koen Martens, Tejas Krishnamohan, and Krishna C.
Saraswat,“Characteristics of surface states and charge neutrality level in Ge”, Appl. Phys.
Lett. vol. 95, p.252101, 2009.
[5] Arun V. Thathachary, K. N. Bhat, Navakanta Bhat, and M. S. Hegde, “Fermi level depinning at the germanium Schottky interface through sulfur passivation”, Appl. Phys.
Lett. vol. 96, p.152108, 2010.
[6] T. Nishimura, K. Kita, K. Nagashio and A. Toriumi, “Long Range Pinning Interaction in Ultra-thin Insulator-inserted Metal/Germanium Junctions”, Silicon Nanoelectronics Workshop, pp.5562590, 2010.
[7] Tomonori Nishimura, Koji Kita, and Akira Toriumi,“Evidence for strong Fermi-level pinning due to metal-induced gap states at metal/germanium interface”, Appl. Phys. Lett.
vol. 91, p.123123, 2007.
[8] Tomonori Nishimura, Koji Kita, and Akira Toriumi,“A Significant Shift of Schottky Barrier Heights at Strongly Pinned Metal/Germanium Interface by inserting an Ultra-Thin Insulating Film”, Appl. Phys. Express. vol. 1, p.051406, 2008.
[9] Masaharu Kobayashi, Atsuhiro Kinoshita, Krishna Saraswat, H.-S. Philip Wong, and Yoshio Nishi,“Fermi level depinning in metal/Ge Schottky junction for metal source/drain Ge metal-oxide-semiconductor field-effect-transistor application”, J. Appl.
Phys. vol. 105, p.023702, 2009.
[10] R. R. Lieten, S. Degroote, M. Kuijk, and G. Borghs, “Ohmic contact formation on n-type Ge”, Appl. Phys. Lett. vol. 92, p.022106, 2008.
[11] Yi Zhou, Masaaki Ogawa, Xinhai Han, and Kang L. Wang, “Alleviation of Fermi-level pinning effect on metal/germanium interface by insertion of an ultrathin aluminum oxide”, Appl. Phys. Lett. vol. 93, p.202105, 2008.
[12] B.-S. Jeong, D. P. Norton, and J. D. Budai, “Conductivity in transparent anatase TiO2
films epitaxially grown by reactive sputtering deposition”, Solid-State Electron, vol. 47, p.2275, 2003.
[13] J.-Y. Jason Lin, Arunanshu M. Roy, Aneesh Nainani, Yun Sun, and Krishna C. Saraswat,
15
“Increase in current density for metal contacts to n-germanium by inserting TiO2
interfacial layer to reduce Schottky barrier height”, Appl. Phys. Lett. vol. 98, p.092113, 2011.
[14] C. H. Lee, T. Nishimura, T. Tabata, S. K. Wang, K. Nagashio, K.Kita, and A. Toriumi,
“Ge MOSFETs Performance: Impact of Ge Interface Passivation”, IEDM Tech. Dig, pp.416-419, 2010.
16
Fig.2.1 In MIGS model, insertion of interfacial layer can reduce MIGS and release FLP. (a) Before. (b) After.
Fig.2.2 Process flow of Ge Schottky junctions and their device structure.
17
Fig.2.3 Band diagram of a Schottky barrier diode on an n-type substrate.
Fig.2.4 A plot of
versus voltage.
-1.0 -0.5 0.0 0.5 1.0
-5x10
1-4x10
1-3x10
1-2x10
1-1x10
10 1x10
1l n ( J/ ( 1 -e
-qV/kT))
(A /c m
2 )Diode Voltage (volt)
18
Fig.2.5 A plot of
versus
Fig.2.6 A plot of the slope versus voltage
0.00310 0.00315 0.00320 0.00325 0.00330 -23.0
-0.12 -0.11 -0.10 -0.09 -0.08
0.80 0.82 0.84
sl o p e
forward bias voltage (volt)
19
(a)
(b)
Fig.2.7 I-V characteristics of metal/Ge junction. (a) metal/n-Ge. (b) metal/p-Ge.
-1.0 -0.5 0.0 0.5 1.0
20
Table 2.1 Ideal factor of Al, Cr, and Au at temperature 30°C~50°C
Fig.2.8 Barrier height versus metal work function
4.0 4.2 4.4 4.6 4.8 5.0 5.2
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
E le c tr o n b a r r ie r h e ig h t (e V )
Metal work function (eV)
21
Fig.2.9 Process flow of Ge Schottky junctions with depinning layer and their device structure.
Fig.2.10 I-V characteristics of Ti/p-Ge junction with different thickness of Al2O3 interfacial layer.
-1.0 -0.5 0.0 0.5 1.0
10
-410
-310
-210
-110
0C u r r e n t d e n si ty , J
(A /c m
2 )Voltage (volt)
0cycle
3cycle
5cycle
8cycle
10cycle
22
(a)
(b)
Fig.2.11 (a) I-V characteristics and (b) barrier height versus metal work function of metal/p-Ge junction with 8cycles Al2O3 interfacial layer.
-1.0 -0.5 0.0 0.5 1.0
10
-310
-210
-110
010
1C u r r e n t d e n si ty , J
(A /c m
2 )Voltage (volt)
Cr (4.5eV) Au (5.1eV) Pt (5.61eV
)4.4 4.6 4.8 5.0 5.2 5.4 5.6
0.0 0.1 0.2 0.3 0.4 0.5 0.6
e le c tr o n b a r r ie r h e ig h t (e V )
Metal work function (eV)
23
(a)
(b)
Fig.2.12 (a) I-V characteristics and (b) barrier height versus metal work function of metal/n-Ge junction with 8cycles Al2O3 interfacial layer.
-1.0 -0.5 0.0 0.5 1.0
10
-310
-210
-110
010
110
2Current density ,J(A/cm2 )
Voltage (volt)
Cr (4.5eV) Au (5.1eV) Pt (5.61eV)
4.4 4.6 4.8 5.0 5.2 5.4 5.6 0.1
0.2 0.3 0.4 0.5 0.6 0.7
Electron barrier height (eV)
Metal work function (eV)
24
Fig.2.13 I-V characteristics of junction with 8cycles ALD Al2O3 interfacial layer at 30 °C ～ 50 °C .(a)Cr/p-Ge. (b) Au/p-Ge. (c) Pt/p-Ge.
25
Fig.2.14 I-V characteristics of junction with 8cycles ALD Al2O3 interfacial layer at 30 °C ～ 50 °C .(a)Cr/n-Ge. (b) Au/n-Ge. (c) Pt/n-Ge.
26
(a)
(b)
Fig.2.15 I-V characteristics of Al/p-Ge junction with GeO2 interfacial layer formed by (a) 550 °C (b) 500 °C.
27
(a)
(b)
Fig.2.16 (a) I-V characteristics and (b) barrier height versus metal work function of metal/p-Ge junction with 500 °C 10s GeO2 interfacial layer.
-1.0 -0.5 0.0 0.5 1.0
28
(a)
(b)
Fig.2.17 (a) I-V characteristics and (b) barrier height versus metal work function of metal/n-Ge junction with 500 °C 10s GeO2 interfacial layer.
-1.0 -0.5 0.0 0.5 1.0
29
(a) (b)
(c) (d)
Fig.2.18 I-V characteristics of junction with 500 °C 10s GeO2 interfacial layer. at 30 °C ～ 50 °C .(a) Al/p-Ge. (b) Cr/p-Ge. (c) Au/p-Ge. (d) Pt/p-Ge.
30
Fig.2.19 I-V characteristics of junction with 500 °C 10s GeO2 interfacial layer. at 30 °C ～ 50 °C .(a) Cr/n-Ge. (b) Au/n-Ge. (c) Pt/n-Ge.
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Fig.2.20 I-V characteristics of Ti/P-Ge junction with different thickness of TiO2 interfacial layer.
-1.0 -0.5 0.0 0.5 1.0
10
-410
-310
-210
-110
010
1C u r r e n t d e n si ty , J
(A /c m
2 )Voltage (volt)
0nm
3nm
6nm
9nm
32
(a)
(b)
Fig.2.21 (a) I-V characteristics and (b) barrier height versus metal work function of metal/p-Ge junction with 6nm TiO2 interfacial layer.
-1.0 -0.5 0.0 0.5 1.0
33
(a)
(b)
Fig.2.22 (a) I-V characteristics and (b) barrier height versus metal work function of metal/n-Ge junction with 6nm TiO2 interfacial layer.
-1.0 -0.5 0.0 0.5 1.0
34
(a) (b)
(c) (d)
Fig.2.23 I-V characteristics of junction with 6nm TiO2 interfacial layer. at 30 °C ～50 °C .(a) Ti/p-Ge. (b) Cr/p-Ge. (c) Au/p-Ge. (d) Pt/p-Ge.
35
(a) (b)
(c) (d)
Fig.2.24 I-V characteristics of junction with 6nm TiO2 interfacial layer. at 30 °C ～50 °C .(a) Ti/n-Ge. (b) Cr/n-Ge. (c) Au/n-Ge. (d) Pt/n-Ge.
36
(a)
(b)
Fig.2.25 Band structure of junctions as TiO2 was regarded as an n-type semiconductor (a) metal/TiO2/p-Ge (b) metal/TiO2/n-Ge
37
Chapter 3
Metal S/D Ge-MOSFET and Conventional N-MOSFET with a Depinning Layer
3.1 Introduction
When the technology node of Si complementary metal-oxide-semiconductor (CMOS) comes to 22nm node, people are looking for new material to replace Si to achieve much higher performance. Ge is one of potential candidates to replace Si due to the higher electron and hole mobility of Ge. Although high hole and electron mobility have been reported for Ge p-FET[1] and Ge n-FET[2-5], the S/D junction technologies for Ge MOSFETs have still some problems such as low solid solubility, and a faster diffusion rate, especially the n-type MOSFET.[6] To make matters worse, Fermi-level was pinned near valance band in Ge, which made the barrier height at metal/n-Ge interface always high and leads to a large series resistance in Ge n-MOSFET.[7-8]
To reduce S/D parasitic resistance, metal S/D could be a promising candidate. But the FLP effect makes the realization of n-Ge metal S/D MOSFET difficult, because the Schottky barrier height (SBH) for electron is high and that for hole is small. Therefore, releasing FLP is necessary to achieve the high performance Ge CMOS. We adopt the depinning layer experience from Chapter 2 to release the FLP on both conventional and metal S/D n-MOSFET.
In this chapter, metal S/D p-MOSFET was fabricated at first. Next, metal S/D n-MOSFET was fabricated with the GeO2 and TiO2 depinning layer. Finally, we tried to use the insertion of TiO2 at metal/n-Ge interface to reduce the parasitic S/D resistance by declining SBH.
38