5.1 Conclusion
In this thesis, the implementation of TDD OFDMA uplink system on TI’s C6416 dig-ital signal processor has been introduced. The implementation was based on the codes from [14] and [15], which dealt with uplink synchronization and FEC encoder/decoder, respectively. We rewrote and integrated those codes into a version that was friendly in block transmission mechanism, which is the method for communication between the host PC and the DSP baseboard. But due to the unknown system software bug, we are unable to run the channel equalizer() on the DSP baseboard yet.
Another part of this thesis was to introduce the optimization techniques in order to accelerate the blocks in our work. We have optimized the modulation, framing/deframing, TX SRRC, FFT/IFFT, and sync blocks. Most of them can achieve real-time rate, but the sync cannot. The computational efficiency was also discussed in this thesis. We computed the ideal complexity needed, and compared it with the practical complexity. The results can remind us that if there still has rooms for further improvements. The efficiencies of TX SRRC, FFT, and sync are 90.94%, 73.18%, and 85.87%, respectively.
The UL synchronization we proposed use the preamble correlation to obtain the sym-bol arriving time instant. Since the values of the preamble of each SS are known by the BS, it can be used as the reference to correlate the received signals. By using this method, we can find the precise timing of the first coming SS. The timing errors are in some degree
to correlated to the channel model. The results are similar to [11].
5.2 Potential Future work
In the realized system, we find that there are several possible extensions that would en-hance the capability and performance.
• The implementation of overall functions in the receiver on DSP should be workable.
The memory allocation problem should be solved.
• The ideal channel equalizer shall be replace by other practical algorithms.
• The BS shall compute the BER and SNR of each user and tune their used subchan-nels to approach the real conditions.
• Strictly speaking, the CPU busmastering interface is not efficient for the DSP base-board communicating with the host PC. We shall consider the streaming interface, another mechanism provided by the Quixote.
• Since there are still many blocks not satisfying the real-time requirement, we can try to partition them on FPGA or other DSP boards.
• Since the communications among DSP baseboards are not applicable in our system, we can not process couples of DSP boards in parallel. If this functionality can be applied, we can consider connecting the source encoder/decoder to our system.
• The integration of other modulation choice (i.e., 16-QAM) in FEC encoder/decoder are not workable yet.
• Analyze the SNR performance of the sync function.
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