5.1 Conclusion
In this thesis, we developed channel estimation schemes for IEEE 802.16a OFDMA downlink transmission. We proposed two kinds of interpolation methods in fre-quency domain which were linear interpolation and 2nd-order interpolation. Alter-nately, we also applied 2-D interpolation and LMS adaptive algorithm in the time domain. The combination of 2-D interpolation and linear interpolation would work efficiently. Because the linear interpolation was of less complexity and its perfor-mance on the whole was almost the same with the 2nd-order interpolation. The 2-D interpolation was more excellent than LMS adaptive algorithm in the time do-main. To such pilot allocation in the IEEE 802.16a OFDMA downlink system, 2-D interpolation would be a good choice.
As to DSP implementation, for the concern of fixed-point C64x DSP, we changed the original floating-point operation to fixed-point 32-bit one. Although this did ac-celerate a lot, there were still limitations in using intrinsics. Therefore, replacing 32-bit fixed-point operation with 16-bit fixed-point operation was a must. Thus, we only had half the original number of bits. To make work correct, we had to be careful with the calculation to prevent from data overflow or underflow. There were three ways to accelerate the DSP execution speed: changing data types, coding style
optimization, and using intrinsics. The total execution cycles of the channel esti-mation scheme have been reduced from 425,630 cycles to 236,871 cycles during the optimization [24]. The realtime rate also raised from 28.46% to 51.14.%. The final result showed our fixed-point 16-bit version can work as well as the floating-point version. It means the decision the bit-field is right enough for our simulation envi-ronment. But with larger the dynamic range of data values, the bit-field must varies at the same time. Besides, most of the functions reach the real time requirements and the rest almost reach it. it shows that the whole system could finish the task in time.
5.2 Future Work
We mentioned the execution cycles of the whole channel estimation scheme have been reduced to 236,871 cycles. There is still distance from the real time. The critical path may be the function Complex Div since executing divider is quite time-consuming. To solve this problem, we may map the received data Y(k) directly to de-64QAM. It means we need to combine the channel estimation output with the de-64QAM block. Meanwhile, the complexity of the de-mapping must be increasing.
It is trade-off. However, it is supposed to be of less complexity than the original one since the added operation in the de-mapping block is multiply. Beside, there are other improvements could be done to accelerate the execution speed.
For the Rayleigh fading channel, we only simulated with fdT=0.01, 0.02. This because the dynamic range of the real channel response varies beyond what we set with the present situation when fdT is larger. Therefore, if we want to simulate with lager fdT, we have to change the bit-field setting in the channel estimation scheme at the same time such as Q6.9, Q7.8, etc.
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