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Chapter1
Introduction and Motivation
Low-temperature-polycrystalline-silicon (LTPS) thin-film-transistors (TFTs) have received much attention in recent years because of their increasing applications in active matrix displays (AMLCDs) [1.1]-[1.5], active matrix organic light emitting displays (AMOLEDs) [1.6]-[1.7], and memory devices [1.8]. Because of their better grain crystallinity, compared with the amorphous counterparts, higher carrier mobility and drive current can be achieved in poly-Si TFTs. The ability of fabricating high-performance LTPS TFTs enables their use in a wide range of new applications. Therefore, further improving the performance of LTPS TFTs is an interesting and important topic.
1-1 An Overview of Low-Temperature-Polycrystalline-Silicon (LTPS) Thin Film Transistors (TFTs)
The study of polycrystalline silicon (poly-Si) thin film transistors (TFTs) fabricated below a maximum temperature of 600°C commenced in the 1980s. The original motivation was to replace quartz substrate with low-cost glass for active matrix display applications. In the beginning, the a-Si:H (hydrogenated amorphous silicon) TFTs were applied as the pixel switching device in the first-generation active matrix liquid crystal displays (AMLCDs). The major advantages of a-Si:H TFT technology are low processing temperature compatible with large-area glass substrate and low leakage current due to the high off-state impedance.
However, because of the lack of short range order, the low carrier field-effect mobility (typically below 1 cm2/V-Sec) of a-Si:H TFTs limited their application to the switching elements only. Integration of driver circuits with display panel on the same substrate is very
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desirable because of the cost reduction in the module and reliability improvement of the system.
More recently, poly-Si TFTs are employed extensively in active-matrix liquid crystal displays because of their superior performance. The effective carrier mobility in poly-Si is significantly higher than that in a-Si, so the devices with reasonably high drive currents can be achieved in poly-Si TFTs. The higher drive-current allows smaller TFTs to be used as the pixel-switching elements, resulting in higher aperture ratio and lower parasitic gate-line capacitance for improved display performance. Previously, poly-Si TFT technology was primarily applied on small, high-definition LCD panels for projection display systems, however, the high processing temperature made it incompatible with commercial large-area glass substrates. With the rapid development of fabrication processes which are compatible with glass substrates in recent years, the manufacture of LTPS TFTs in AMLCDs on large-are substrates attracts more attentions. Modification of process procedure for enhancing TFT performance and reducing fabrication cost become an important issue in the fabrication of LTPS TFTs on large-area glass substrates.
Compared to the ultra-large scale integration (ULSI) process technology, the processes anddevice structures of LTPS TFTs are similar with metal-oxide-semiconductor field-effect-transistors (MOSFETs). The noticeable difference between LTPS TFTs and MOSFETs is that the former has to be performed at relatively low temperatures in order to be compatible with glass substrates. Due to this feature, only a-Si or poly-Si channels can be achieved on the glass substrate and the mobilities of a-Si and poly-Si are both much lower than that of c-Si (single-crystal silicon), which is widely used in conventional MOSFETs.
Therefore, how to further increase the mobility of the low-temperature TFTs is one of the most important challenges. Among various process issues, the crystallization of a-Si thin films has been considered to be the most important process for fabricating high-performance
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LTPS TFTs. The crystallized poly-Si thin films always serve as active layer (i.e., channel) in the poly-Si TFTs. As a result, the quality of crystallized poly-Si films profoundly affects the performance of the poly-Si TFTs. In polycrystalline materials, most of defects are present in the grain boundaries. Enlarging grain size by various crystallization methods, such as solid phase crystallization (SPC), laser crystallization, and metal-induced crystallization (MILC), can reduce the grain boundaries and effectively promote the quality of poly-Silicon. The performance of devices can be improved through the high-quality poly-Si formed by crystallization technologies. Furthermore, other low-temperature process technologies of fabricating LTPS TFTs, such as gate dielectric formation, dopant activation, defect passivation, and device structures, are also essential for producing high-performance LTPS TFTs.
Finally, novel structure design is another approach to fabricate high-performance poly-Si TFTs. This technique focuses on the reduction of the electric field near the drain junction, and thus suppresses the device’s off-state leakage current. Many structures including multiple channel structures, offset drain/source, lightly doped drain (LDD), gate-overlapped LDD, field induced drain and vertical channel have been proposed and investigated intensively.
1-2 Motivation for improving Low-Temperature-Deposited Gate Dielectric Used in LTPS TFTs
In the recently, the gate dielectric scaling down trended toward of the physical limitation (~1.0nm for SiO2) for International Technology Roadmap for Semiconductors (ITRS) [1.9]. It extend a number of fundamental problems such high leakage current、low oxide breakdown voltage and low mobility…etc.
For TFTs, the key parameters of the LTPS TFTs are：(1) High mobility, (2) Low threshold voltage, and (3) High driving current and Low leakage current at high operate
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voltage. These are for demand of that to realize system-on-panel (SOP)、integrating driving ICs on the glass substrate and drive the liquid crystal. Using a thin dielectric can improve the driving current of TFTs. Similar to MOSFETs, however, the conventional gate dielectric (i.e.
SiO2、Si3N4 ) for small dimension TFTs also need to decrease the thickness. Although thinning down the gate oxide can increase the drive current of TFTs, however, the quality of low-temperature silicon oxide is not good enough, it results in higher gate leakage current.
However, the low-temperature-deposited oxide used in LTPS TFTs always exhibits poorer physical and electrical quality, such as high interface trap density, high gate leakage and low breakdown field, compared with high-temperature thermal grown oxide used in VLSI MOSFETs. Consequently, thicker gate oxide has to be used to prevent the high gate leakage current.
1-4 Why do we use High- κ materials?
In order to preserve the physical dielectric thickness while increasing the gate capacitance, several new high-κ materials, including Al2O3, Ta2O5 were proposed [1.10]-[1.11]. Among them, Al2O3 TFTs improvement is not sufficient due to the κ value is not high enough. On the other hand, the Ta2O5 TFTs induce higher gate leakage current due to its narrow band-gap.
In thesis, we fabricated the LTPS TFTs with High-κ gate dielectrics deposited by AVD system, including HfO2, HfSiOx and HfAlOx. Mainly, in addition to show the lower threshold voltage，we want to discuss the influence of the different composition ratios of HfSiOx and HfAlOx films and reliability. Moreover, we hope to increase the driving current, decrease the threshold voltage of High-κ device and have high gate capacitance capability compared with conventional devices. Therefore, we found the better High-κ dielectric for LTPS TFTs that will show higher mobility, alleviated VTH roll-off, improved subthreshold
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swing, and increased on/off current ratio for n-channel Poly-Si TFTs.
Finally, we used the advanced materials as same as the LTPS TFTs on MOSFETs for thinner films. Then, the structure and electrical properties were discussed about various composition ratios influence.
1-5 Organization of the Thesis
In this thesis, the advanced High-κ materials were employed to fabricate the high-performance low-temperature polycrystalline silicon thin film transistors and metal- oxide-semiconductor field-effect transistors.
In Chapter 2, a new AVD system was the metal-organic chemical vapor deposition (MOCVD), dedicated to the deposition of the advanced high-κ films, was introduced briefly.
Afterwards, we focused on the study in which HfO2 HfSiOx and HfAlOx films were deposited under different pulse ratios using AVD system. Both structural and electrical characterizations of the High-κ films were presented. The effects of important deposition parameters, including the deposition temperature, the chamber pressure, oxygen gas flow, deposition frequency, and the composition adjustment, on the physical properties of as-deposited thin films were examined. Then the thermal stability of the High-κ films was studied with the help of post-deposition annealing (PDA) at high temperature.
In Chapter 3, high performance and low-temperature-compatible n-channel polycrystalline-Silicon TFTs were using High-κ materials.
In Chapter 4, high performance MOSFETs was using High-κ materials.
Finally, conclusions as well as future prospects for further research were given in Chapter 5.
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Chapter2
Characterizations of High- κ Films Deposited by Atomic-Vapor Deposition
2-1 Introduction
As the dimensions of complementary metal oxide semiconductor (CMOS) devices are scaled into the nanometer regime, the gate dielectric thickness must also decrease to maintain a value of capacitance to reduce short channel effects and to keep device drive current at an acceptable level. The Semiconductor Industry Association's (SIA) International Technology Roadmap for Semiconductors (ITRS) indicates that by the years 2003-2005, the equivalent oxide thickness (EOT) of the gate dielectric decreases steadily to thinner than 1nm. Its leakage current under normal operation bias falls into the direct tunneling regime. For future generations of metal-oxide-semiconductor field-effect transistors (MOSFETs), the current gate oxide layer (SiO2 or SiOxNy) will need to be replaced with a new material possessing a higher dielectric constant (κ >κSiO2=3.9).
High-κ materials are employed to increase the physical thickness of the gate insulator while maintaining the same EOT and gate capacitance, thus reduces significantly the tunneling leakage current. Although many High-κ materials are proposed to replace the conventional silicon dioxide (SiO2) as gate insulator, Hafnium dioxide (HfO2) is the most promising candidate for its excellent advantages, such as a suitable dielectric constant (~25) [2.1], high band-gap energy (~ 5.9eV), and suitable tunneling barrier height for both electron and hole (>1eV). However, HfO2 is easily crystallized during deposition or following annealing processes, and crystallization increases the leakage current via grain boundaries. In order to improve the relatively low crystallization temperature of around 600°C of pure HfO2,
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alloying HfO2 with SiO2 and Al2O3 has been proposed [2.2]-[2.3]. Since their silicon or aluminum binary oxides, such as HfSiOx and HfAlOx, retain an amorphous structure after high temperature treatment, these binary oxides are now the most promising candidates to become the gate dielectric for next-generation MOSFETs [2.4]-[2.5].
Recently, High-κ materials have been investigated using several deposition techniques including physical vapor deposition (PVD) [2.4], atomic layer deposition (ALD) [2.9], plasma enhanced chemical vapor deposition (PECVD) [2.10], and jet vapor deposition (JVD) [2.11].
Although physical vapor deposition (PVD) is a simple technique for depositing new materials for evaluation in an academic organization, it may cause severe plasma damage to the electrical devices and is not preferred by industries because of poor step coverage and thickness uniformity. Chemical vapor deposition (CVD) has the advantages of uniform thickness over large substrate areas and good conformal step coverage. In contrast to ALD, it is relatively easy to dope the HfO2 using CVD, which may be necessary for future gate dielectrics.
In this chapter, we employed the new atomic vapor deposition (AVD) system to deposit the High-κ films. The AVD system would be introduced briefly in section 2-2. Afterward, we focused on a study in which HfO2, HfSiOx and HfAlOx films were deposited under different pulse ratios using AVD system. We present both structural and electrical characterizations of the High-κ films. First of all, the deposition and evaluation of HfO2 thin films have been performed in section 2-3. In addition, we would hope to deposit simultaneously a stack structure to suppress interfacial layer growth. For example, a stack structure deposited two different High-κ dielectrics for a top gate oxide was HfO2 film and a under gate oxide was HfSiOx film.
In the second part, the Si atoms incorporation into HfO2 films were investigated various composition ratios and these results of HfSiOx films were discussed in section 2-4. Finally,
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the Al atoms incorporation into HfO2 films were investigated various composition ratios and these results of HfAlOx films were discussed in section 2-5.
2-2 Overview of Atomic-Vapor Deposition (AVD) System
Figure 2-1 illustrates the schematic diagram of the AVD system. The main parts of the AVD system contain an AIXTRON horizontal reactor and a liquid-delivery TRIJET-TM vaporizer. Metal-organic precursors are used as the source of the High-κ film and kept at room temperature in liquid phase in a stainless tank. The precursor would be injected into the vaporizer via high-speed electro-mechanical valves and the injector plays the important role to control the injection amounts of the precursors. The injected amounts of the precursors can be controlled exactly by adjusting the injection numbers and opening time of individual injectors. In our experiment, the opening times of the injectors were all fixed at 0.8 msec. The injection periods and pulses can be adjusted to control the thickness and composition of the deposited films. The liquid precursor was injected to the vertical vaporizer and transferred from liquid type to gas type immediately. The temperature of vaporizer at 170℃could be introduced according to the kind of precursors. Argon gas would be used as carrier gas to carry the vaporized precursor into the reactor through the showerhead. The process gas, oxygen in our experiment, would be heated first in gas-box and then mixed with vaporized precursors in the showerhead. Finally, the mixed gases flowed to the process reactor and film deposition would take place on the hot substrate. The deposition parameters, including deposition temperature, chamber pressure, oxygen gas flow, injection frequency and pulse numbers, could be fine-tuned to obtain the adaptable films in different device applications.
Among all process parameters, the substrate temperature is the key issue to affect the quality of the as-deposited films.
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2-3 Structure and Electrical Characterizations of HfO
2and HfO
2+HfSiOx-IL
2-3.1 Experiment
HfO2 films were deposited by liquid-injection atomic-vapor deposition (AVD) system and the liquid precursor was Hafnium(Tert-Butoxy)2(mmp)2, (Hf[OC(CH3)3]2(mmp)2, mmp：
OC(CH3)2CH2OCH3), which was dissolved in octane to make a 0.05 M solution. The evaporation temperature of vaporizer was 170℃. Argon gas was used as the carrier gas, with a flow rate of 200 sccm, and oxygen as the oxidant with a flow rate of 1300 sccm. Substrate temperatures were 500℃, and the chamber pressures were 5 mbar. Prior to the deposition, the 6-inch silicon substrates were treated with standard RCA clean. After the cleaning process, the HF-treatment was to immerse wafers into a 100:1 diluted HF solution and then spun dry without rinse in DI water. Subsequently, wafers were put immediately into MOCVD for HfO2
and HfO2+HfSiOx-IL films deposition to prevent the native oxide formation. The thickness of film was controlled by the injection pulse numbers. In addition, we split two cases of HfO2 film thickness for 40 nm (CaseⅠ) and 4 nm (CaseⅡ). Subsequently, caseⅠwas post deposition annealing (PDA) at 600℃ for 24h in N2 ambient of poly-Si TFT device and case
Ⅱ was rapid temperature annealing (RTA) at 900℃ for 30sec in N2 ambient of MOSFET device. The deposition rate was extracted by measuring the thickness of thick HfO2 film with N&K 1500 analyzer and anther thin film with an elliposmeter.
2-3.2 Material Properties Extraction
After film deposition, post deposition annealing (PDA) was performed on all samples to investigate its impact on material properties and electrical characteristics of HfO2 films. The fundamental physical properties of these films were analyzed by many techniques, such as
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x-ray photoelectron spectrum (XPS), grazing incidence x-ray diffraction spectrum (GI-XRD) and high resolution transmission electron microscopy (HRTEM).
In addition, the electrical characteristics of the HfO2 films were extracted from the
capacitors, low-temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) and metal-Oxide-semiconductor field-effect transistors (MOSFETs) device. For electrical analysis,
a precision impedance meter (Agilent 4284) was used for C-V measurements and a semiconductor parameter analyzer (Agilent 4156C) was used for I-V measurements.
2-3.3 Structural Characterizations of HfO
2Films by XPS Analysis
In caseⅠ, chemical characterizations of HfO2 and HfO2+HfSiOx-IL films were accomplished by x-ray photoelectron spectroscopy (XPS) utilizing monochromatic and standard Al x-ray source. The results are shown in Figures 2-2. In caseⅡ, the results are shown in Figures 2-3. Detected elements in thin films are hafnium (Hf), oxygen (O), and carbon (C). In order to avoid the undesirable carbon contamination on the sample surfaces, XPS analyses were also performed with ion milling. Negligible damage by low energy ions during depth profiling could be assumed since no significant shift of the binding energies is observed. It is found that the relative intensity of C1s signals decreases drastically after sputtering.
Then, we would check Si spectra of our samples to compare with Si standard data base to correct XPS signals. This result is reasonable due to the fact that all air-exposed materials will have a thin film deposition, composed primarily of hydroxide (i.e., alcohol-type, C-OH units).
After removing this thin layer, the signals originating from purer HfO2 can be obtained. This phenomenon shows that the composition of HfO2 good chemical binary at the caseⅠand Ⅱ.
We calculated the atomic area of XPS data and sensitivity factor to extract the Hafnium and oxygen atomic ratio. For HfO2 film, Hf/O composition ratio = 1/2.3 in Table 2-1.
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2-3.4 Chemical Bonding and Composition of HfO
2Films by XRD Analysis
After annealing at 600℃ for 24h in N2 ambient. Figures 2-4 to 2-5 show the GI-XRD spectra of the HfO2 film and HfO2+HfSiOx-IL films, more sharp peaks, which are identified to come from monoclinic polycrystalline structure, become more visible. The dominate phases of monoclinic polycrystalline structure are (110)、(-111)、(111)、(200)、(220). Among them, the intensity of (110)、(-111)、(200)、(220) phases at one layer HfO2 film were larger than HfO2+HfSiOx-IL stack structure. On stack structure, the plane of (111) that density is bigger than the other phases. The HfSiO-IL aids to slightly suppress the formation of monoclinic phase in HfO2 film.
After rapid temperature annealing at 900℃ for 30sec in N2 ambient. CaseⅡ in Figure 2-6 shows the monoclinic phases as same as the caseⅠ.
The disadvantages of polycrystalline thin films in the device applications are the large leakage current, device characterization lead to degrade.
2-3.5 Structural Images of HfO
2Films by TEM analysis
Figure 2-7 shows the images of cross-sectional TEM for the HfO2 sample deposited at 500°C and the samples with subsequent post-deposition annealing at 600 ℃ for 24h in N2 ambient, respectively. The TEM samples of poly-Si TFT devices and MOSFET devices were fabricated by focus ion beam (FIB) method.
The test structures (gate-electrode/gate-dielectric/poly-Si channel) are included in the samples of TFT devices. In partⅠ, the lighter contrast is near the HfO2/poly-Si channel interface. This interfacial layer is thought to be a Si-rich Hf silicate according to many previous reports, even though this speculation can be hardly identified by any compositional analysis method. The dark contrast is purer HfO2 film. The total physical thickness, the
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individual thickness of HfO2 film and interfacial layer are 48.9nm and 1.0nm, respectively summary in Table 2-4. By the way, other problem to the upper interface between gate-electrode and HfO2 was rough. This could be caused by contact badly and induced leakage paths.
In partⅡ, Figure 2-8 shows the images of cross-sectional TEM for the stack structure. A bottom layer HfSiOx film deposited100A at 500°C. Subsequently, a upper layer HfO2 film deposited 300A at 500℃. The samples with subsequent post deposition annealing at 600℃
for 24h in N2 ambient. The total physical thickness, the individual thickness of HfO2 film, HfSiOx-IL and interfacial layer are 37nm, 6.5nm and 1.0nm, respectively summary in Table 2-4. Figures 2-9 , 2-11, which were identified by TEM energy-dispersive spectroscopy (EDS) in Table 2-5 lists the element ratios of Hf, Si and O in bright (Spectrum1) and dark (Spectrum2) regions separately.
Figure 2-12 shows the images of cross-sectional TEM for caseⅡ. The light region was an interface layer between HfO2/Si. Physical thickness of HfO2 film and IL were 3.3nm and 2.0nm, respectively summary in Table 2-6.
2-4 Structure and Electrical Characterizations of HfSiOx Films 2-4.1 Experiment
In this section, we focus on the deposition and evaluation of HfSiOx films. HfSiOx films were deposited by liquid-injection atomic vapor deposition (AVD) and the liquid precursors were Hf[OC(CH3)3]2(mmp)2 and Si[OC(CH3)3]2(mmp)2 respectively; both are dissolved in octane to make a 0.05M solution. Form the reference process parameters for HfSiOx thin
In this section, we focus on the deposition and evaluation of HfSiOx films. HfSiOx films were deposited by liquid-injection atomic vapor deposition (AVD) and the liquid precursors were Hf[OC(CH3)3]2(mmp)2 and Si[OC(CH3)3]2(mmp)2 respectively; both are dissolved in octane to make a 0.05M solution. Form the reference process parameters for HfSiOx thin