In this thesis, our contribution of this work is that we implement a 3D placement flow
including timing analysis. We assign cells and TSV cells by partitioning-based placement and
greedy algorithm in global placement. The TSV cells assignment always satisfy alignment
constraint. Then simulated-annealing refines the timing performance. At last, we remove
overlap during detail placement. The experimental results show that our methodology in 3D
ICs has better wirelength performance than 2D ICs and less T N S in some benchmarks.
In the future, the most important thing is that models a more precise TSV delay model
for 3D timing analysis. This is essential for delay calculation. The accurate TSV cell model
is urgent in physical design of 3D ICs.
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