Conclusion and Future Work

In this thesis we have proposed a detailed router that supports the data compression algorithm, LineDiff Entropy algorithm, for MEBDW systems. In the beginning we have introduced such system including the significance, the expectation, and the problem it confronts. And then we did some calculation to estimate the lack in throughput needs a compression ratio larger than 450.

After the complete expression of the algorithms, the results of experiments were listed. And they’ve shown that for LineDiff Entropy algorithm, proposed detailed router performs much better than the router without our modification in compression ratio while maintaining decompression rate. And the estimated goal 450 is reached after applying our algorithm.

And there is another important contribution in our research. We’ve mentioned that there is no such research in solving throughput problem in MEBDW system from the aspect of circuit physical design. Our research proved that this is a field worth investment.

But there also exists something more to improve. For routing part, routability should be further promoted to around 100% to meet the requirements in manufacturing these days. And this could be done if we introduce a structure which is able to dynamically select, defuse and reroute. Such structure could automatically selects wires causing routing congestion or making LineDiff Entropy performs poorly. And then these wires might be canceled in order to route other wires first, to further improve routability or CR.

As for industrial manufacturability, there is actually an important phase we ignored in this thesis called Electron-beam Proximity Correction (EPC). This phase is necessary

because the patterns might have a distortion after written by E-beam emitter.

Figure 5.1 Latent image simulation procedures. [17]

Figure 5.1 shows the simulation of a pattern distortion. In this flow, the original layout is represented by some standard polygons, and then they’re taken convolution with a Point Spread Function (PSF) which can be derived from Gaussian function [18]

to get the energy map. And finally after filtered by a threshold, we get the image on the right in Figure 5.1, which is the actual pattern that will be written. We can see such a variation that even causes circuit short.

This is why the EPC process is needed. But we can also comprehend that after EPC, layout patterns could have skewed shapes which cannot be compressed easily by any data compression algorithm.

Another work might be worth researching is a brand new data compression algorithm which can cooperate with our proposed router or with little adjustment.

Because the basic idea of proposed router is to take advantage of the repetition of patterns, there should be some more ways to further improve compression performance with it.

REFERENCE

[1] Chin-Khai Tang, Ming-Shing Su, and Yi-Chang Lu,

“

Signal Processing Letters, Vol. 20, No. 7, July 2013, pp. 645-648.

[2] P. Petric, C. Bevis, A. Brodie, A. Carroll, A. Cheung, L. Grella, M. McCord, H.

Percy, K. Standiford, and M. Zywno, “REBL nanowriter: Reflective Electron Beam Lithography,” Proc. SPIE, vol. 7271, Alternative Lithographic Technologies, 727107, Mar. 2009, doi: 10.1117/12.817319.

[3] Ming-Shing Sua, Kuen-Yu Tsaia, Yi-Chang Lua, Yu-Hsuan Kuoa, Ting-Hang Peia, and Jia-Yush Yenb, “Architecture for next generation massively parallel maskless lithography system (MPML2),” Proc. SPIE, Vol. 7637, Alternative Lithographic Technologies II, 76371Q, Apr. 2010, doi: 10.1117/12.846444.

[4] V. Dai, “Data Compression for Maskless Lithography Systems: Architecture, Algorithms and Implementation,” Ph.D. dissertation, University of California, Dept. Electrical Engineering Computer Science, Berkeley, CA, USA, 2008.

[5] Jeehong Yang, “Lossless Circuit Layout Image Compression Algorithm for Multiple Electron Beam Direct Write Lithography Systems,” Ph.D. dissertation, University of Michigan, 2012.

[6] Cheng-Chi Wu, Jensen Yang, Wen-Chuan Wang, Shy-Jay Lin, “An Instruction-based High-Throughput Lossless Decompression Algorithm for E-Beam Direct-Write System,” Proc. SPIE, vol. 9423, Alternative Lithographic Technologies VII, 94231P, Mar. 2015, doi: 10.1117/12.2085278.

[7] Jacob Ziv, Abraham Lempel, "A Universal Algorithm for Sequential Data Compression". IEEE Transaction on Information Theory, Vol. IT-23, No. 3, May

1977, pp. 337-343.

[8] Laung-Terng Wang, Yao-Wen Chang, and Kwang-Ting Cheng, “Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon),” 1st Edition,

Elsevier Inc., 2009, Chapter 12, pp. 687-749.

[9] Lee, C.Y., and Whippany, N. J., “An Algorithm for Path Connections and Its Applications,” IEEE IRE Transactions on Electronic Computers, Vol. EC-10, No.

3, Sept. 1961, pp. 346-365.

[10] Peter E. Hart, Nils J. Nilsson, Bertram Raphael, “A Formal Basis for the Heuristic Determination of Minimum Cost Paths,” IEEE Transactions on Systems Science

and Cybernetics, Vol. 4, No. 2, July, 1968, pp. 100-107.

[11] Minsik Cho, Yongchan Ban, and David Z. Pan, “Double Patterning Technology Friendly Detailed Routing,” in IEEE/ACM International Conference on

Computer-Aided Design, 2008, pp. 506-511.

[12] Shao-Yun Fang, “Lithography Optimization for Sub-22 Nanometer Technologies,” Ph.D. dissertation, National Taiwan University, Graduate Institute of Electronics Engineering, Taipei, Taiwan, 2013.

[13] Jhih-Rong Gao, and David Z. Pan, “Flexible self-aligned double patterning aware detailed routing with prescribed layout planning,” Proceedings of the ACM

international symposium on International Symposium on Physical Design, 2012,

pp. 25-32.

[14] Soukup, J., “Fast Maze Router,” 15th Design Automation Conference, 1978, pp.

100-102.

[15] Akers, Sheldon B., “A Modification of Lee’s Path Connection Algorithm,” IEEE

Transactions on Electronic Computers, Vol. EC-16, No. 1, Feb., 1967, pp. 97-98.

[16] 2013 International Technology Roadmap for Semiconductors: http://www.itrs.net/

[17] S.-Y. Lee and B. D. Cook, “PYRAMID-A Hierarchical, Rule-Based Approach Toward Proximity Effect Correction-Part I: Exposure Estimation,” IEEE

Transactions on Semiconductor Manufacturing, Vol.11, No. 1, 1998, pp. 108-116.

[18] Shy-Jay Lin, Pei-Yi Liu, Cheng-Hung Chen, Wen-Chuan Wang, Jaw-Jung Shin, Burn J. Lin, “Influence of Data Volume and EPC on Process Window in Massively Parallel E-Beam Direct Write,” Proc. SPIE, vol. 8680, Alternative Lithographic Technologies V, 86801C,March, 2013, doi: 10.1117/12.2010865.