In this thesis, a sliding mode controller is proposed to compensate for the nonlinear friction force of the mini VCM which is applied to CCM. Stick slip oscillation is avoided and steady state error can be designed in arbitrarily small by pole placement of the sliding mode state equation. The effectiveness of the controller is firstly proved by the simulation results.
The experimental results then demonstrate that the transient response is less than 10ms, no stick slip limit cycle oscillation occurs in steady response, and repeatability performance is also satisfactory. Consequently, the proposed control scheme works well and is reliable.
A PC-based experimental environment is also introduced. It is not only cost effective but also of high calculation power. Control algorithm validation can be more efficient by using it.
References
[1] B. Bona and M. Indri, “Friction compensation in robotics: an overview”, Proc. of the 44th IEEE Conference on Decision and Control, and the European Control Conference 2005, Seville, Spain, December 12-15, 2005.
[2] B. C. Kuo and F. Golnaraghi, Automatic Control Systems, 8th Edition, John Wiley &
Sons, Inc.
[3] C. C. de Wit, H. Olsson, K. Å ström, and P. Lischinsky, “A new model for control of systems with friction,” IEEE Trans. on Automatic Control, vol. 40, no. 3, pp. 419–425, 1995.
[4] J. Chen, A. Prodić, R. W. Erickson and D. Maksimović, “Predictive digital current programmed control,” IEEE Trans. on Power Electronics, vol. 18, no. 1, pp. 411-419, January 2003.
[5] B. C. Baker, "Anti-aliasing, analog filters for data acquisition systems", AN699, Microchip Technology, Inc, 1999.
[6] J. J. E. Slotine and W. Li, Applied Nonlinear Control, Pearson Education Taiwan Ltd, 1991.
[7] Information Technology -AT Attachment with Packet Interface - 5(ATA/ATAPI-5).
[8] H. C. Yu, T. Y. Lee, S. J. Wang, M. L. Lai, J. J. Ju, D. R. Huang and S. K. Lin (2005),
“Design of a voice coil motor used in the focusing system of a digital video camera,”
IEEE Trans. on Magnetics, vol. 41, no. 10, pp. 3979-3981, 2005.
[9] H. C. Yu, T. Y. Lee, S. K. Lin, S. J. Wang, M. L. Lai, J. J. Ju and D. R. Huang, “Low power consumption focusing actuator for a mini video camera,” Journal of Applied Physics, vol. 99, no. 8, art. no. 08R901, 2006.
[10] S. K. Lin, C. M. Wang, and S. J. Wang, “Design and implementation of antihandshaking position control for a voice coil motor,” Journal of Applied Physics, vol. 103, no. 7, art. no. 07F128, 2008.
[11] S. Southward, C. Radcliffe, and C. MacCluer, “Robust nonlinear stick-slip friction compensation,” ASME Journal of Dynamic Systems, Measurement and Control, vol.
113, no. 4,pp. 639–645, 1991.
[12] Jhih-Da Hsu, Ching-Lung Tsai and Ying-Yu Tzou, “Design and implementation of a voice-coil motor servo control IC for auto-focus mobile camera applications,” Power Electronics Specialists Conference 2007. PESC 2007.
[13] Taiwan R.O.C. Patent I287906.
[14] G. Ellis, Control System Design Guide, 2th Edition, ACADEMIC PRESS.
[15] Ned Mohan, Tore M. Undeland, William P. Robbins, Power Electronics, 3th Edition, John Wiley & Sons, Inc.
Appendix A : Control algorithm design flow
As shown in Figure 23, the first step of designing control algorithm is extracting the simulation model for the control plant. Ideally, we hope to get a complete mathematical model which describes all physical characteristics of the plant. But generally this ideal model is not available, only approximated model can be derived. So that experiments must be performed before claiming the control algorithm design is done, because control algorithm deals with the real control plant in experiment.
The developed control algorithm was firstly validated by simulation, the experiment then was performed. It can save a lot of time if validation experiment is performed on PC-based experimental environment before implementing it on FPGA. Following explains the improvement. Assume there are 3 kinds of control algorithms are evaluated and last one is the best choice. Also assume that it needs 1 day to implement algorithm in C and 10 days to implement algorithm on FPGA when m file algorithm is available. There will be 3 iterations before being ready for ASIC design. The time of performing algorithm validation is 1+1+1+10=13 days while adopting PC-based experimental environment. The time of performing algorithm validation without PC-based experimental environment is 10+10+10=30 days. It shows the proposed design flow can save 17 days in this case. If the target of experiment is not preparing for ASIC design, but just validating the algorithm with real control plant, which is mostly the case in school, then the tedious FPGA implementation thing can be ignored. We do think this is quit helpful for graduate students, because they are able to spend more time on algorithm studying.
We also recommend performing co-simulation of Simulink, ModelSim and PSIM, as shown in Figure 22, when implementing control algorithm with hardware description language (HDL). With this co-simulation environment, all functional bugs can be fixed easily because ModelSim can show all internal signals for the HDL design. On the contrary, debugging functional problem of HDL design in FPGA hardware is very difficult. Firstly, only few suspected signals can be routed to the IO pads because of the limitation of IO pads number. Not being able to show all suspected signals at once on a screen increases the
difficulty of debugging. It usually requires multiple iterations of pulling out suspected signals before a functional bug is fixed. Secondly it takes time to synthesis the HDL design to FPGA.
It is really time consuming to debug functional problem of HDL design on the FPGA hardware by comparing doing this on the co-simulation environment.
Once FPGA validation is finished, the HDL design of the control algorithm is ready for ASIC implementation. And the people taking care of ASIC implementation can know nothing about algorithm things, but familiar with the ASIC design flow. Mostly, developing algorithm is the strength of the people staying in the educational fields. And ASIC implementation is the strength of the people staying in the industry fields. By adopting the proposed design flow, people in the school is able to release a “ready for ASIC design” HDL to a company for prototype and production. So that people in these two fields can cooperate seamlessly and be win-win partner.
Figure 30 : Cosimulation environment for Simulink, Modelsim and PSIM.
Figure 31 : The design flow of developing control algorithm.
Extract plant model for Simulink or PSIM
Migrate the controller (mfile) from Simulink to C
Design controller
Validate controller by Simulink (Cosim with PSIM if needed)
Validate controller on PC-based experimental
environment
Implement controller on FPGA with Verilog
Validate controller by cosim of Simulink and Modelsim
Synthesis controller to FPGA
Validate controller by FPGA experimental environment
Ready for ASIC design OK
OK
OK
OK
NG NG NG NG
Appendix B : PATA specification brief
The 40-pin ATA connector, with pin definition and signal description, and “Register transfer protocol” are shown here as a quit reference for implementation. Figure 25 shows the ATA connection orientation and pin number assignment. It can be seen that there are 2 keys for the orientation identification: 1) number 20 is an empty pin and 2) the housing has a gap.
Table 2 shows the signals assignment for 40-pin ATA connector. The letter “-“ of signal name indicates that the signal is low active. Figure 24 and Table 3 shows the timing of PIO register transfer protocol. It should be remarked that the high level means assertion in Figure 24. For example, DIOR- is low active. Assertion means that it is in low voltage. With this hardware regarding information, we can design a FPGA which is able to communicate with the PATA port on the motherboard.
Table 2 : Signals assignment for 40-pin ATA connector Signal name Connector contact Signal name
RESET- 1 2 Ground
DD7 3 4 DD8
DD6 5 6 DD9
DD5 7 8 DD10
DD4 9 10 DD11
DD3 11 12 DD12
DD2 13 14 DD13
DD1 15 16 DD14
DD0 17 18 DD15
Ground 19 20 (keypin)
DMARQ 21 22 Ground
DIOW- 23 24 Ground
DIOR- 25 26 Ground
IORDY 27 28 CSEL
DMACK- 29 30 Ground
INTRQ 31 32 reserved
DA1 33 34
PDIAG-DA0 35 36 DA2
CS0- 37 38
CS1-DASP- 39 40 Ground
tC NOTES
1 Device address consists of signals CS0-, CS1- and DA(2:0) 2 Data consists of DD(7:0).
3 The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is to be extended is made by the host after tA from the assertion of DIOR- or DIOW-. The assertion and negation of IORDY are described in the following three cases:
3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released prior to negation and may be asserted for no more than 5 ns before release: no wait generated.
3-3 Device negates IORDY before tA. IORDY is released prior to negation and may be asserted for no more than 5 ns before release: wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated and DIOR- is asserted, the device shall place read data on DD(7:0) for tRD before asserting IORDY.
tB
Figure 32 : Timing of PIO register transfer protocol.
Table 3 : Timing value assignment for PIO register transfer protocol Register transfer timing parameters Mode 0
ns
Mode 4 ns
Note
t0 Cycle time (min) 600 120 1,4
t1 Address valid to
DIOR-/DIOW-setup (min) 70 25
t2 DIOR-/DIOW- pulse width 8-bit (min) 290 70 1
t2i DIOR-/DIOW- recovery time (min) - 25 1
t3 DIOW- data setup (min) 60 20
t4 DIOW- data hold (min) 30 10
t5 DIOR- data setup (min) 50 20
t6 DIOR- data hold (min) 5 5
t6Z DIOR- data tristate (max) 30 30 2
t9 DIOR-/DIOW- to address valid hold (min) 20 10 tRD Read Data Valid to IORDY active
(if IORDY initially low after tA)
(min) 0 0
tA IORDY Setup time 35 35 3
tB IORDY Pulse Width (max) 1250 1250
tC IORDY assertion to release (max) 5 5
NOTES
1 t0 is the minimum total cycle time, t2 is the minimum DIOR-/DIOW- assertion time, and t2i is the minimum DIOR-/DIOW- negation time. A host implementation shall lengthen t2 and/or t2i to ensure that t0 is equal to or greater than the value reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.
2 This parameter specifies the time from the negation edge of DIOR- to the time that the data bus is released by the device.
3 The delay from the activation of DIOR- or DIOW- until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the register transfer cycle is completed. If the device is not driving IORDY negated at the tA after the activation of DIOR- or DIOW-, then t5 shall be met and tRD is not applicable. If the device is driving IORDY negated at the time tA after the activation of DIOR- or DIOW-, then tRD shall be met and t5 is not applicable.
4 ATA/ATAPI standards prior to ATA/ATAPI-5 inadvertently specified an incorrect value for mode 2 time t0 by utilizing the 16-bit PIO value
Figure 33 : ATA connector orientation and pin number assignment.
1 39
2 40
Appendix C : Verilog behavior coding of second order Butterworth filter
`timescale 1ns/1ns //module butterworth;
module butterworth_top(
in, out );
input [15:0] in;
output [15:0] out;
reg [15:0] out;
parameter iir_a = 7616, iir_b= 15232, iir_c= 7616, iir_d= -14929, iir_e= 6856;
reg [31:0] temp32,temp32_2, temp32_3, iir_o_n, iir_o_n_1, iir_o_n_2;
reg [15:0] iir_in_n_1, iir_in_n_2;
wire [15:0] iir_in_n = in;
initial begin
temp32 = 0; temp32_2 = 0; temp32_3 = 0; iir_o_n = 0; iir_o_n_1 = 0; iir_o_n_2 = 0;
iir_in_n_1 = 0; iir_in_n_2 = 0;
#10;
Forever begin
temp32 = $signed(iir_a) * $signed(iir_in_n);
temp32 = $signed(iir_b) * $signed(iir_in_n_1) + $signed(temp32);
temp32 = $signed(iir_a) * $signed(iir_in_n_2) + $signed(temp32);
temp32_2= $signed(iir_d) *
$signed(downcase_f32_17_to_f16_17(iir_o_n_1));
temp32_2= $signed(iir_e) *
$signed(downcase_f32_17_to_f16_17(iir_o_n_2)) + $signed(temp32_2);
temp32_3= $signed(iir_d) *
$signed(downcase_f32_17_to_f16_2(iir_o_n_1));
temp32_3= $signed(iir_e) *
$signed(downcase_f32_17_to_f16_2(iir_o_n_2)) + $signed(temp32_3);
iir_o_n=case_f32_21_to_f32_17(temp32)
-case_f32_30_to_f32_17(temp32_2);
out=downcase_f32_17_to_f16_0(iir_o_n);
#25_000; //sampling time iir_in_n_2 = iir_in_n_1;
iir_in_n_1 = iir_in_n;
iir_o_n_2 = iir_o_n_1;
iir_o_n_1 = iir_o_n;
end //forever end //initial
function [15:0] downcase_f32_17_to_f16_17;
input [31:0] i;
begin
downcase_f32_17_to_f16_17 = {i[31],i[14:0]};
end
endfunction
function [15:0] downcase_f32_17_to_f16_2;
input [31:0] i;
begin
if((~|i[31:30]) || (&i[31:30]) )
downcase_f32_17_to_f16_2 = i[30:15];
else begin if(i[31])
downcase_f32_17_to_f16_2 = 16'h8000;
else
downcase_f32_17_to_f16_2 = 16'h7fff;
end end
endfunction
function [15:0] downcase_f32_17_to_f16_0;
input [31:0] i;
begin
downcase_f32_17_to_f16_0 = {i[31],i[31:17]};
end
endfunction
function [31:0] case_f32_21_to_f32_17;
begin
case_f32_21_to_f32_17 = {{4{i[31]}},i[31:4]};
end
endfunction
function [31:0] case_f32_30_to_f32_17;
input [31:0] i;
begin
case_f32_30_to_f32_17 = {{13{i[31]}},i[31:13]};
end
endfunction
function [31:0] case_f32_15_to_f32_17;
input [31:0] i;
begin
case_f32_15_to_f32_17 = {i[31],i[31:13]};
if((~|i[31:29]) || (&i[31:29]) )
case_f32_15_to_f32_17 = {i[31],i[28:0],2'b00};
else begin if(i[31])
case_f32_15_to_f32_17 = 32'h8000_0000;
else
case_f32_15_to_f32_17 = 32'h7fff_ffff;
end end
endfunction endmodule
作者簡歷
個人資料
姓 名：蔡慶隆 (Ching-Lung Tsai)
生 日：民國 61 年 01 月 12 日
性 別：男
專 長：數位控制、順滑模態控制、IC 設計
學 歷
2007.9~2009.7 國立交通大學電機學院電機與控制學程碩士 1990.9~1994.6 國立中山大學電機系
1987.9~1990.6 高雄市立高雄高級中學