In this thesis, we proposed a novel TLB architecture for asynchronous embedded processors. In addition, we also modeled it with Balsa HDL which is a CSP-based asynchronous HDL. We demonstrated how to transfer the proposed architecture into asynchronous circuits. In this chapter, the conclusions and future works will be summarized.
5-1 Conclusions
The computing devices have enormous changing for the past decades. Only recent years, the embedded systems and mobile devices have been becoming the major trend in computing devices. For the past years, because early applications of these systems are simple, no extra complex operating systems are needed. However, new embedded systems and mobile devices have begun to support very complex operating systems, such as Windows® Mobile and embedded Linux. Google even tries to provide very powerful software stack platform based on embedded Linux called Android [107]. All these new applications need very efficient supporting for embedded operating systems. Traditional design needs specific microcontroller or processor to execute OS, and other DSP or accelerator processor to boost computing performance. Recently, some designs try to provide an alternative solution. These designs integrate both general purpose processor and DSP or accelerator processor into a single processor, such as cores of Blackfin [108] and TILE processors [109]. All these new trends demonstrate the importance of OS in embedded systems or handheld devices. In order to provide high performance address translation from virtual address to physical address of modern OS, the high efficient TLB design is needed. The TLB misses cause serious performance degradation on modern processors. In addition, the context switching under the multiprogramming OS may cause this problem even more seriously. However, only some studies focus on the context switching issue for embedded processors. In our work, we presented an alternative TLB design to reduce the miss rate in context switching for embedded processors.
In addition, it is widely known that synchronous circuit has some disadvantages, such as clock skew, higher power consumption, worse-case performance, and poor reusability.
However, asynchronous circuit can easily address these problems. In addition, asynchronous circuit has higher reliability and robustness than its synchronous counterparts. In fact, all these are all critical issues for embedded processors or microcontrollers. But it’s very hard to implement digital systems with asynchronous circuits.
In our work, we implemented the proposed TLB controller for the proposed TLB architecture with asynchronous circuits. We implemented our proposed TLB controller with the 4-phase bundled-dada handshaking protocol. The bundled-data model was implemented with Balsa HDL which is a CSP-based asynchronous HDL. With the Balsa HDL, we can focus on the asynchronous architecture and algorithm designs without considering too much on the handshaking protocol issues. In addition, because several target handshaking protocols are supported by the Balsa tools, you don’t need to implement each HDL model for each handshaking protocol. Thus, higher flexibility can be provided. Unfortunately, the synthesized result shows that total equivalent gate count of the TLB controller without memory is 688,560.
That’s really not cheap. However, we also found that the CU and prefetch control parts are not very expensive. It costs only 1,441 equivalent gates, but the TLB memory parts costs 687,119 equivalent gates. That’s not only because we modeled lots of functionalities for this part but also lots of extra memory control circuitry is added by Balsa tool suite. However, we still successfully demonstrated an advanced asynchronous TLB controller than other related works. Thus, the following items are the main features of the proposed asynchronous TLB
Modeled with Balsa HDL, the TLB controller can be synthesized into handshaking protocols supported by Balsa framework.
Simple and clear interface definitions can make the designed be used easily.
Unambiguous separation of each part in real asynchronous design makes verifications of the asynchronous TLB controller easier.
5-2 Future Works
In this thesis, we propose an alternative TLB architecture to reduce miss rate in context switching for asynchronous embedded processor. As mentioned in section 3-2, to estimate miss rate more accuracy the simulator should be integrated with OS. Therefore, new simulator model should be developed for further study. In addition, as mentioned in section 3-1, the performance of TLB not only relies on miss rate but also miss penalty. That’s means the execution time should be taken into consideration. However, because lack of information of processor architecture and memory system, it’s not very easy to estimate it directly. The design should be placed into a real processor.
As mentioned before, most asynchronous processors today are very simple; thus, most of them do not support virtual memory. In our work, we hope to provide a general asynchronous TLB architecture that can be implemented in asynchronous processors. That’s why we modeled our design with Balsa HDL. With high-level asynchronous HDL, the design can be synthesized into all supported handshaking protocols by Balsa tool suite. However, the Balsa tool suite cannot provide the real TLB memory; thus it should be implemented separately. In this work, we only simply use latches to replace the real TLB memory for verification. It’s not reasonable. Thus, this part should be carefully handled in our future work. In addition, as the analysis in section 4-4, besides the functionalities we modeled to control behavior of the TLB memory the extra circuitry added by Balsa tool suite is very huge. The part really should be redesigned manually in the future.
Finally, our goal is to design our own asynchronous RISC core with virtual memory support for embedded systems or handheld devices. In fact, we hope to design asynchronous-based SoC or MPSoC with our own asynchronous processor core. As mentioned in section 2-2-3, there are some studies of asynchronous interconnections and GALS. In fact, the clock issue has been becoming one of the most critical issues in large SoC designs. As mentioned in section 1-2, ideally, asynchronous circuits may make software
“OOP”-style design on hardware possible. Imaging, without the global clock issue, designing SoC might be a little like playing the LEGO® bricks. Ideally, each asynchronous IPs can be plugged in the design if they “talk” the same “handshake protocol.” That’s why we hope to design our own asynchronous processor core. The design of asynchronous TLB is one of the
critical parts of the asynchronous processor core. In order to verify our future processor core more formally, we’ll suggest a new asynchronous processor design flow that can support not only architecture exploration but also facilitate hardware/software co-design. We’ll discuss this topic in the next section.
5-3 Verification Issue for future work
In traditional synchronous based design, the verification can be easier than that of asynchronous ones. You can verify your design based on the “clock.” That means that you can verify the status of the design based on the clock cycles. Figure 5-1 shows a very simplified VLSI design flow. The design ideas are described in cycle-based functional specification descriptions. Traditionally, the functional specification can be described with C programming language. Thus, the cycle-based simulator can be used to prove the design ideas.
Then, the design will be implemented in RTL/gate-level design. To verify the implementation, the two models will be verified via cycle-by-cycle cross-verification. Finally, the design can be transferred into layout. Certainly, the cycle-based equivalence checking should be done between RTL/gate-level design and layout. On the contrary, without the global clock, each part of the design may work in its own speed and it’s not easy to make sure if the design operates correctly in any specific time. It will be even worse that the operation times of the same component may be also different depending upon the input. That’s especially on most DI/QDI designs. You can be very sure what status should be of your design at 10th cycle, but how can you do the same thing on system without clock? Imaging in a 2-phase bundled data design and given a specific time, how can you make sure the status should be? As mentioned in section 2-2-2, in such systems each part of the design may begin to operate whether the request or acknowledge signals are rising edge or falling edge. Verifications of different models of asynchronous circuits may also be a good research topic.
We have already pointed out that lots of new issues should be carefully dealt with in developing embedded processors. Because most of these problems can be resolved with asynchronous circuits, that’s why we put lots of efforts in developing asynchronous processors. In addition, because of some new application requirements, new features should be supported by these processors. However, it’s important to do some architectural explorations before these features can be supported. Thus, we’ll suggest a design flow that can be used to design new asynchronous embedded processors from architectural exploration to functional verification. Figure 5-2 shows our new design flow. We’ll introduce the use of architecture description language (ADL). LISA will be selected as our design tool [110].
That’s not only because LISA is the most popular and successful ADL but also it’s a mixed
structural and behavioral ADL. Thus, the design described with LISA can be used to generate simple toolchains including (compiler), assembler, linker, and simulator. It can also be used to generate RTL of Verilog HDL. Thus, hardware/software co-design can be easily achieved.
CoWare® Inc. now provides a complete GUI IDE based LISA development environment called CoWare® Processor Designer [111]. With CoWare® Processor Designer, it makes LISA easy to learn and use. The first, the design specification should be implemented with LISA descriptions manually. Then the CoWare® Processor Designer can be used to generate toolchains and simulator. It should be noted that in order to achieve the goal of hardware/software co-design the application software can be developed simultaneously. In addition, if the designed architecture is described in structural model, the RTL can also be generated. Though the RTL model generated is not a very efficient implementation, it still can be used as reference synchronous model for evaluation. In fact, after simulator and toolchains can be generated, the performance of designed architecture can be roughly estimated. Then the generated simulator can be used as golden model in order to do cross-verification with new designed asynchronous processor. However, because it’s impossible to do clock-by-clock cross-verification with asynchronous circuits, we suggest using the “instruction-based”
cross-verification. That means we can compare the execution results instruction-by-instruction. With this design flow, we can develop our new asynchronous embedded processor more effectively.
Figure 5-1: Simple VLSI design flow
Figure 5-2: Our asynchronous processor design flow
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