This paper has presented efficient and effective packing and analytical placement algorithms for large-scale heterogeneous FPGA design.
Our packing algorithm is composed of three stages to handle different struc-tures of heterogeneous components and datapath blocks. Our packing provides a more placement-friendly netlist than VPR’s, which gives a great potential for placers to achieve significant quality improvement. A V-shaped framework is proposed to enhance the scalability while considering more exact design constraints than exist-ing works. Moreover, our wirelength-driven analytical placement algorithm applies effective nonlinear optimization techniques and utilizes the regularity of the datap-aths to achieve scalability and high quality. A complex-block-alignment function is proposed to better handle the heterogeneity, and a multilevel framework is applied to further enhance the scalability of our placement algorithm.
We compared our packer and placer with the state-of-the-art FPGA CAD tool, VPR. The experiments were conducted on a set of modern large-scale FPGA benchmarks, Titan23 benchmark suites. The experimental results have shown that our approach achieves a 199.80× speedup, compared to the VPR’s latest packing flow (VPR 7.0). Meanwhile, our placer achieves a 3.07× speedup with 6% shorter wirelength, compared to the VPR’s latest placement flow. Furthermore, the overall
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flow (packing and placement) achieves a 18.30× speedup with 6% shorter wirelength, compared to the VPR’s latest packing and placement flow.
There are three future research directions: the analytical FPGA placement problem with segmented-length routing architecture, the analytical FPGA placement problem considering timing delay, and FPGA routing. We detail the future research directions below.
First of all, the pre-fabricated programmable routing architecture of modern FPGAs is segmented and there are several types of length. Hence, the way to predict routing and estimate routability in FPGA placement could be very different from that in ASIC placement. Furthermore, the current wirelength model might not be accurate enough for the routing estimation. As a result, how to utilize the various routing resources effectively and combine the estimation with an analytical placement framework have become a new challenge.
Secondly, in addition to wirelength and routability, timing is another critical issue in FPGA placement. Timing has been well explored in ASIC placement.
The timing issue in FPGA design, however, still has lots more to work on because multiple routing resources could lead to different delays, which makes timing harder to predict.
Finally is the FPGA routing. Because the existing open-source FPGA router demonstrated poor scalability when facing large-scale circuits, FPGA routing is also a research direction on the scalability issue. Furthermore, understanding the FPGA routing could also help to build a quick routing forecast during placement.
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