In previous chapter, we have presente owever,
if we
gestion reduction algorithm that can
d wirelength reduction technique. H
only consider wirelength minimization, it may produce lower routability result.
In this chapter, we will present two congestion reduction techniques to try to produce routable circuit: cell sorting based congestion reduction and congestion-avoided cell shifting. In cell sorting based congestion reduction, we use two-pin nets difference as score to sort cell position to solve horizontal congestion. In congestion-avoided cell shifting, we will shift the cells in the congested bins to further reduce congestion.
5.1 Cell Sorting Based Congestion Reduction In this section, we present cell sorting based con
fast reduce horizontal congestion to improve routability. In our cell sorting based congestion reduction algorithm, we will select cells in each congestion bins as segment, and we will compute difference of two-pin nets (diff_TPN) for each cell in the segment. The definition of diff_TPN is the number of two-pin nets that connect to its right side subtracts the number of connection to the left side. In order to define right two-pin nets (right_TPN) and left two-pin nets (left_TPN), we must set left and right boundary of the segment first. The left boundary is position of the leftest cell and right boundary is position of the most right cell. If the position of the connecting cell of the two-pin net exceeds right boundary, then this two-pin net is a right_TPN. If the position of the connecting cell of the two-pin net exceeds left boundary, we call such two-pin net a left_TPN. Then we can compute diff_TPN using number of the right two-pin nets subtracts number of the left two-pin nets. Finally, we sort diff_TPN in
separate each neighbor cells using average free sites in the segment.
Fig. 10. Illustration of Cell Sorting Based Congestion Reduction method. (a) Original circuit before Cell Sorting; (b) New circuit after Cell Sorting.
Figure 10 shows an example of cell sorting based congestion reduction. Figure 10(a
estion reduction only considers horizontal wires and solve
) is the original circuit, and the new circuit after cell sorting based congestion reduction is shown in Figure 10(b). In Figure 10(a), the two-pin nets of C1, C2, C3 and C4 are thin real lines, thin dashed lines, bold real lines and bold dashed lines respectively. The cell C1 has three two-pin nets include two right_TPNs and one left_TPN. The diff_TPN of C1, C2, C3 and C4 are 1, 0, -2 and -3. Then we sort this number of sequence and get order of cell be C4, C3, C2 and C1. The result shows in Figure 10(b) and we can observe that the congestion of new circuit is less than the congestion of original circuit.
Cell sorting based cong
s horizontal congestion. However, vertical congestion may be increased by sorting. In order to avoid such situation, we will check the number of pins in the global bins after sort. Figure 11 displays the flow of cell sorting based congestion reduction. Firstly, we will select a congested segment do cell sorting based congestion reduction. Then we will sort the cell by diff_TPN. If number of pins exceeds maximal pin number in each bin, the sorting result will be rejected. Finally, the information of cells and two-pin nets would be updated.
Fig. 11. Design flow of Cell Sorting Based Congestion Reduction 5.2 Congestion-Avoided Cell Shifting
The goal of congestion-avoided cell shifting is to reduce congestion by shifting the cells in the congestion region to non-congestion region. This method has two important issues: how to select cells and where to be placed. In section 5.2.1, we will describe simulated evolution-based cell selection. In section 5.2.2, cell shift with avoiding congestion algorithm will be introduced.
5.2.1 Simulated Evolution-based Cell Selection
SILK [9] is a simulated evolution-based router, it presented a rip-up and re-route technique for detailed routing. The simulated evolution technique scores each creature in the current population, and determines the survival rate of each creature in the next generation. SILK scores each net in generation using routing violation and path quality and normalized the scores to 0.1-0.9. Then SILK generates a random number between 0.0 and 1.0. The normalized score of nets are greater than their random number are be marked. After comparing all nets, the marked nets are put into queue.
The order of nets in the queue decreases from higher normalized score to lower normalize soccer. Thus, SILK avoids falling local optimal, it let nets with lower cost
In our work, we use congestion, wirelength, and number of pins to generate cells in congestion region as follow:
(1) congestion of two-pin nets of cell i, then congestion of the two-pin net is average of congestion of bins that the two-pin net go through, #two−pin nets is total number of
two-pin nets, is square of difference between
and , is average of congestion of all two-pin nets of
In Equation (1), the first part is average congestion and variation. The variation helps our placer to detect which cell may have larger congestion of two-pin nets when they have the same average congestion.
Figure 12 displays the pseudo code of simulated evolution-based cell selection.
In the beginning, we calculate score of cells by Equation (1), all score are normalized to 0.1-0.9 and generator generates the random between 0.0 and 1.0. If the cells with normalized score that are larger than their random number will push queue. Finally, we order cells in queue from higher normalized score to lower normalized score. The cell with higher normalized score will be shifted first. In next section, we describe the function: CongstionAvoidShifting(cell i).
Fig. 12. Simulated Evolution-based Cell Selection Algorithm 5.2.2 Cell Shifting with Avoiding Congestion
The objective of congestion-avoided cell shifting is to reduce congestion by shifting the cells in the congestion region to non-congestion region. However, where should the cells be replaced remains a problem. In this section, we will show the cost function we use to decide where cell be shifted first. Then, we will describe the function CongestionAvoidedShifting(cell i).
For each cell i, the cost function for congestion-avoid cell shifting is defined as follows:
(2)
,where α , β , α , '' β , 'γ ,and ω are user-defined constants, ' is the distance between original position and new
position of cell i, , , , and represent
difference of two-pin nets in left-direction, right-direction, up-direction, and down-direction respectively.
_ _
distance(org pos, new pos) _
diff left diff _right diff _up diff _down
Fig. 13. Example of Difference of Two-Pin Nets
Figure 13 represents how to calculate , and
in nets re n with c cell4; cell 5 has two-pin
cost functio , we can calculate between two ce _
diff left , _diff right , _diff up
_ . In Figure 13(a), cell 1 has two-p latio ell 2, cell 3, and nets relation with cell 6 and cell 7 respectively. The dashed line shows congestion region and the other region is non-congestion region. The shadowed region with slanted lines is bounding box of cells that have two-pin net relation. In each shadowed region with slated line, we use two arrows to represent possible direction when routing between cells with two-pin net relation. So, cell 1 has three bounding box and six arrows of bounding box from cell 1 to other cells. If we want to know change of difference of two-pint nets after swapping cell 1 and cell2.
The cell 5 will swap with cell 1 and calculate difference of two-pin nets of cell 5 using new position that shows in Figure 13(b). Finally, diff _left , _diff right , _diff up , and _diff down can be calculate through subtract
13(b) from number of arrows of Figure 13(a) in left-direction, right-direction, up-direction, and down-direction respectively. In this example, diff _left ,
_
diff right , _diff up , and diff _down equal 2, -1, 0, and 1 respectiv
n lls or a cell and a space. If we calculate
cost between a cell and a space, the difference of four directions are produced arrows of four directions. The cell with higher cost can be swapped with a space or a cell and reduce congestion with higher opportunity because this cell with less two-pin nets
diff down
ing number of arrows of Figure
ely. In this
connected with it.
Figure 14 shows the pseudo code of the proposed CongestionAvoidedShifting Func
Fig. 14. CongestionAvoidedShifting Function
tion. TFS_j represents total free sites in cell j placed row of cell i shifting range, width_i represents width of cell i, and width_j is width of cell j. If free sites are enough or cell i can swap with cell j, the gain is calculated (line 4-6). After calculating and recording all gain, we select maximal gain. If maximal gain is larger than zero, we update position and two-pin nets of shifted cells and rip-up and reroute two-pin nets of shifted cells. Finally, we update information of bins (line 9-13).
Chapter 6
Experimental Results
he proposed placer was implemented in C/C++ language on AMD Opteron 2.6G
Dragon 3.0.1 [10] and mPL-R [3]. The results are given in Table II–III. In Table II, we show results including total run tim
T
HZ with 16GM memory. IBMv2 benchmarks [9] were used in our experiment.
The characteristics of these benchmarks, including number of cells, number of nets, core utilization, white space and routing layers, are shown on Table I..
Table I Characteristic of IBM Version 2 Benchmarks
We compare our result with several state-of-the-art academic tools, including
e and routed wirelength(rWL). For rWL, Our Placer is better than Dragon about 4.2% after replacing by Our Placer. We compare the same items with mPL-R in Table III. The rWL of Our Placer yields 2.3%
improvement compared to mPL-R. For overflow of pre-routing, Our Placer is better
than Dragon 6.4% and better than mPL-R 6.6% after congestion reduction.
Table II Comparison of Placement Results of Dragon and Our Placer
Table III Comparison of Placement Results of mPL-R and Our Placer
Chapter 7 Conclusions
In this paper, we propose a placer that improves routed wirelength and routability.
Our work presents three methods including reduced-wirelength cell shifting, enhanced local re-ordering, and cell rearrangement by bipartite matching to minimize routed wirelength and two methods including cell sorting based congestion reduction and congestion-avoided cell shifting to reduce congestion of global routing in placement stage. Experimental results shows our placer can improve routed wirelength on IBMv2 benchmark with other placer placement results. The routed wirelength (rWL) of our placer yield 4.3% and 2.5% compared to Dragon and mPL-R respectively.
Chapter 8 Bibliography
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