As shown in Figure 3-1, basically, the fabrication process flow can be break into six parts: mesa isolation; ohmic contact making; T-shaped gate making; gate recess; passivation and contact via hole; air bridge.
3.1 Wafer Cleaning
Before any fabrication step, every wafer must go through the cleaning procedure. Every wafer was immersed in ACE for 5 minutes, and then followed by 5 minutes in IPA to remove contamination from the wafer surface.
After, the wafer was blown dry using nitrogen.
3.2 Mesa Isolation
As the name suggested, mesa isolation is to isolated devices from each other. A mesa isolation can force the current to flow under the gate metal from source to drain. This is very important because if the some of the current flow between source and drain without passing under the gate metal, the current will become a parasitic resistance, which can degrade the RF performance of the device.
The active region is defined by mesa isolation. In addition, parasitic capacitance, parasitic resistance, leakage current and back-gating effect can all be reduced with effective isolation. A successful isolation provides sufficient insulating area to form passive elements such as transmission lines, capacitors,
pads, etc.
Typically, etching, ion bombardment isolation and selective implantation are the three methods of achieving mesa isolation. Among these three methods, mesa etching is the simplest one. First, the mesa pattern was defined by photolithography. The mesa was etched using phosphoric solution;
later, the depth was measured using α-step. For this study, the ideal depth is around 3000Å. In addition, the etched profile could be checked with SEM (scanning electron microscopy).
3.3 Ohmic Contact
The purpose of an ohmic contact on semiconductor is to allow the electrical current to flow in and out of the semiconductor. It is a low resistance junction formed between metal and semiconductor interface. An ohmic contact should obey the ohms law; in another word, it should have a linear I-V characteristic either under forward or reverse bias. Ohmic contact is very important because a successful one can lead to better device performance. With lower contact resistance, power consumption will decrease. In order to create a low resistance ohmic contact, the metal-semiconductor interface region should be heavily doped. In addition, an ohmic contact should be stable over time and temperature and should have as little resistance as possible.
The pattern of the ohmic contact with an undercut profile was defined using photolithography method. After, the sample was send to O2 plasma descum to remove residual photoresist and dipped into HCl solution to remove
oxide. Finally, an e-gun evaporation system was used to deposit Au/Ge/Ni/Au onto the sample. After ohmic formation, the contact resistance was measured by TLM (transmission line method).
The purpose of the germanium in the ohmic metal is for GaAs doping during alloy. The nickel is like a wetting agent which prevents the AuGe metal from “balling up” during alloy. The Au/Ge alloy is commonly used because it forms low contact resistance ohmic and has good reliability.
3.4 T-Shaped Gate
commonly used because an e-beam system allows high resolution, excellent registration, and can automatically generate undercut resist profile for the ease of lift-off.After the gate open had been defined on resist, recess was to be performed. Usually, wet etching was used for this task; although dry etching could also be used, it tends to cause ion bombardment damage that degrades the device performance. A recessed gate offers several advantages. First of all, when the gate is placed under the surface depletion of surrounding material,
the surface depletion will not be able to restrict the current flow during forward gate bias. Secondly, when the channel is thinner, the breakdown is increased. Finally, gate recess can increase the breakdown and reduce source-gate resistance.
Citric acid (C.A.) based solution was used during recess process to etch the cap layer. After, HCl solution was used to etch the schottky layer until the target current was reached.
Gate length is a crucial parameter of determining the performance of a device. Shorter gate can give higher gain and lower noise; in addition, high frequency devices depend greatly on short gates. However, there is one problem with short gate and that is the raise in gate resistance due to the reduction in cross-sectional area of the gate. A major solution for this problem is a T-shaped gate. This kind of gate will have a large cross-sectional area at top while maintaining a remaining a short gate length that is contacting the wafer.
To fabricate a T-shaped gate, a dual layers photoresist technique can be used. Traditionally, the bottom layer is poly methyl methacrylate (PMMA) and the top layer is copolymer (PMMA-MAA). Since the sensitivity of copolymer is higher than PMMA, the opening for copolymer will be greater than that of the PMMA; therefore, a T-shaped gate can be formed. This dual layer process will be discussed in more detail later on.
In this study, instead of the traditional PMMA and PMMA-MAA, chemical amplified resist was used as the e-beam resist. Conventionally,
chemical amplified resist is used for deep UV lithography due to its high sensitivity. High sensitivity is not the only advantage of a chemical amplified resist. The exposed and unexposed areas have solubility with great difference;
therefore, resolution is high.
3.5 Passivation and Contact Via
An III-V device can easily be affected by surface conditions especially at the gate area. As the size of gate shrinks, particles and contaminations can easily damage a device. Passivation can protect the device from these damages during handling, processing and data measuring. The material used for passivation is usually SiNx. In this research, the passivation layer was grown by PECVD and the precursors used are SiH4/Ar, NH3, and N2.
After passivation, via holes was formed using photolithographic method and etched using RIE. The via holes were opened at source and drain areas for interconnects. The gases used for SiNx etching was CF4 and O2.
3.6 Air Bridge
In order for source, drain and gate to be on the same plane, there will be places where the gate will cross either drain or source since eventually all the gates must be connected. However, when gate and drain are in contact, parasitic capacitance will be formed and cause problems during operation.
Therefore, usually, the gate only crosses with source. A bridge suspended in the air over the gate is used to connect the sources. There is nothing but air between the source and the gate; hence, it is called an air bridge, see Figure
dielectric constant, with air the parasitic capacitance can be low and can carry substantial current.
Photolithography and electro plating are the two major steps in air bridge formation. After the first layer pattern was defined using photolithography, Ti/Au/Ti was been deposited on the wafer. Then second layer pattern was formed using photolithography. Finally, the air bridge metal, gold in this case, was electro-platted. After gold had been electro-platted, the photoresist and Ti/Au/Ti layer were removed separately; the only remaining was the electro-platted air bridge.
Gold is usually the material used for air bridge. Gold has many advantages: high conductivity, inert to oxidation and acidic environment, ductile, good formability etc. Since the adhesion between gold and the wafer surface is poor, a thin layer of titanium is usually deposited. By doing so, the adhesion can be improved.
Air bridge is the last step for the front-side process. After finishing this last step, RF characteristics of the device can be measured.