The following description would show the fabrication process of our research. A 4-in (100) n-type silicon wafer which thickness is about 180 µm was used as bulk. First, native oxide is removed by DHF for 2 minutes, and then metal removal by HPM for 20 minutes at 80℃, after that native oxide is removed by DHF again, shown in Fig. 2.10 ,oxide was grown by HNO3 for 5 minutes next, then wafer was dipped in KOH for 30minutes at 80℃ for texture, shown in Fig. 2.11, after ionic metal
removal by HPM for 20 minutes at 80℃, and native oxide removal by DHF, 36 nm Si3N4, was deposited at front side of wafer, shown in Fig.
2.12, then wafer was dipped in NaOH for 5 minutes for rear side polish, shown in Fig. 2.13, after all these treatment, Si3N4 was removed by BOE(buffer oxide etching) for 10 minutes, metal removal by HPM for 20 minutes at 80℃ and native oxide removal by DHF were performed, shown in Fig. 2.14. All process we have just mentioned was performed in ITRI, after that we adopted HDP-RIE and the first photolithography to etch silicon material at polish side to form align-key we needed for the following photolithography process. Next, blocking oxide 500 nm was deposited at polish side by PECVD, shown in Fig. 2.15, and then second photolithography was used to define p+ emitter region, then the wafer was dipped in BOE solution to etch the oxide which covered the emitter region, then p+ emitter was formed by ion implant(B11, 5e15, 10 keV) , shown in Fig. 2.16, then wafer was dipped in BOE again to remove all oxide remained, shown in Fig. 2.17, after this blocking oxide 500 nm was deposited at polish side, shown in Fig. 2.18, n+ BSF region was defined by third photolithography, after blocking oxide which covered n+ region was removed by BOE and photoresist was removed, ion implant was
adopted to form n+ BSF region(P31, 5e15, 30 keV) , shown in Fig. 2.19, then the rest blocking oxide was removed by BOE, shown in Fig. 2.20, all photolithography process was performed in NFC. Then the dopant annealing was performed at 1000℃ for 1 minute in O2, shown in Fig.
2.21. Then BOE was used again to remove oxide at both side, shown in Fig. 2.22, after that PECVD blocking oxide 500 nm was deposited at polish side, shown in Fig. 2.23, and we sent wafer for POCl3 diffusion, we set 5 conditions for POCl3 diffusion, 650℃ for 20 minutes, 675℃
for 20 minutes and 700℃ for 20 minutes, 850℃ for 20 minutes with drive in and wet oxide growing 10 minutes and 30 minutes, shown in Fig.
2.24, after this we did not remove PSG , instead, we directly deposited PECVD SiNx 90 nm on PSG as anti-reflection layer, shown in Fig. 2.25, then removing blocking oxide at polish side by BOE, shown in Fig. 2.26.
Next, 10 nm ALD Al2O3 deposition was adopted at polish side, then the device was dealt with annealing immediately, we still have 2 conditions for Al2O3 annealing(300℃, 400℃, 30 minutes in O2 ambient) , shown in Fig. 2.27, then we deposited PECVD SiNx 150 nm on Al2O3 layer, shown in Fig. 2.28. Fourth photolithography was used to define emitter passivation region, both SiNx and Al2O3 at polish side was removed by
BOE except for the region protected by photoresist, shown in Fig. 2.29, then we used PECVD SiNx deposition again to passivate undiffused region and n+ region, thickness is 150 nm, shown in Fig. 2.30. Fifth photolithography was used after PECVD SiNx deposition to define contact region, BOE was applied for contact etching, shown in Fig. 2.31, then the following process was metal deposition, we use Titanium and Aluminum stack for metal finger, deposited by E-gun, Ti thickness is 10 nm and Al thickness is 1000nm, shown in Fig. 2.32, Al deposition was applied at once after Ti deposition, there was no chamber vent between two process to avoid Ti oxidation. Sixth photolithography was applied for metal finger formation, shown in Fig. 2.33, then Al etching solution and BOE were used to remove Al an Ti that we did not wanted, sintering at 380℃, 20 minutes in N2 ambient was assumed to improve contact of metal and silicon and fabrication process is completed. The SEM micrograph of random pyramids texture surface are shown in Fig. 2.34, Fig. 2.35 and the picture of device is shown in Fig. 2.36.
Fig. 2.1 Definition of Air Mass [2.1]
Fig. 2.2 AM1.5G solar spectrum [2.2]
I L
current
voltage
Fig. 2.3 Circuit model of series resistance
Fig.2.4. Circuit model of shunt resistance
voltage current
v oc
I
scI
mpV
mpFig. 2.5 explanation of Fill Factor
Fig. 2.6 explanation of External Quantum Efficiency
Fig. 2.7 Loss Mechanism
Fig. 2.8 QE3000 [2.3]
n-type
Fig. 2.9 WCT-120 [2.4]
Fig. 2.10 silicon bulk after clean treatment
Fig. 2.11 KOH etching for texture formation
Fig. 2.12 SiNx deposition as protection layer
n-type
Fig. 2.13 rear side polished by NaOH etching
Fig. 2.14 SiNx removed by BOE etching and clean
Fig. 2.15 blocking oxide deposition at rear side
Fig. 2.16 emitter definition and Boron implantation
Fig. 2.17 blocking oxide removed by BOE etching
Fig. 2.18 blocking oxide deposition
n-type
P +
emitter
n+
n+
Fig. 2.19 back surface field definition and Phosphorus implantation
Fig. 2.20 blocking oxide removed by BOE etching
n-type
P +
emitter
n+
n+
Fig. 2.21 annealing at 1000℃ for 1 minute in O2 ambient
Fig. 2.22 oxide removed by BOE etching
Fig. 2.23 blocking oxide deposition at rear side
Fig. 2.24 POCl3 diffusion at different temperature
Fig. 2.25 SiNx deposition at front side as ARC
Fig. 2.26 blocking oxide removed by BOE etching
Fig. 2.27 ALD Al2O3 deposition at rear side
Fig. 2.28 SiNx capping layer deposition at rear side
Fig. 2.29 emitter passivation definition with BOE etching
Fig. 2.30 SiNx passivation deposition
Fig. 2.31 contact definition
Fig. 2.32 metal deposition
n-type
n
+n
+ P+emitterAl/Ti
Al2O3 Al2O3
Fig. 2.33 metal finger definition
Fig. 2.34 scanning electron microscope (SEM) micrograph of random texture surface
Fig. 2.35 scanning electron microscope (SEM) of texture surface cross section
Fig. 2.36 image of front side and back side of device