4.2.0 Overview of Experimental Results
All results are shown in tabular form with discuss under the tables; besides, the improvement rate of each comparison relative to the proposed design are also provided in percentage.
The result of critical path delay in worst case, area cost at critical timing, and power consumption will be reported and compared at the following sections.
4.2.1 Comprehensive Comparison
This section provides all experimental results with a comprehensive comparison compared among the proposed core ACARM7, ARM7 Compatible Processor (Korus 2005) and ARM7TDMI. As can be seen in the Table4.2, the process technology used by the proposed core ACARM7 and ARM7-Korus2005 are both 0.18um while ARM7TDMI uses 0.25um technology; therefore, all comparisons in the following sections will be normalized to 0.18um technology for correctness.
The row named “Other characteristics” of the Table4.2 shows some specific characteristics which are unique to each of different cores; in addition, the row named “Note” indicates some attention notes to clear some misunderstandings might be made. The p.s.1 of the note is that all the experimental results of ARM7TDMI are come from a TSMC 0.25um hard macro; on the hand, p.s.2 and p.s.3 mentions that both benchmarks for power estimation of ACARM7 and ARM7TDMI are based on Dhrystone with temperature 25C, but the former is in voltage condition of 1.8V and the later is in 2.5V. The last note reminds readers that all experimental results are obtained in worse case except power estimation is measured in typical case.
All the information obtained from Table4.2 like timing, area, and power will
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be analyzed and compared among the 3 different cores in the following sections.
Comprehensive Comparisons among Three Different Cores
Proposed Core
Other characteristics No Thumb;
DFT supported
No DFT supported
Hard Core No DFT supported p.s.1:TSMC 0.25um hard macro
p.s.2:Dhrystone,1.8V,Temp=25。C p.s.3:Dhrystone,2.5V,Temp=25。C Note
All experiment results are measured in worse case except power estimation is in typical case Table4.2 Comprehensive comparison among 3 different cores
4.2.2 Timing Comparison
This section discusses the timing comparison among 3 different cores and the performance of ARM7TDMI obtained from Table4.2 should be normalized to 0.18um technology first by using an equation below:
55 X (
After normalization, the performance of ARM7TDMI is normalized to 76MHz.
However, it is still lower than 90MHz of ARM7-Korus2005 and 110MHz of
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ACARM7. The proposed design has such a high performance because it uses a high-performance IPs like Fong-adder and Ling-Multiplier and implements the ISA without Thumb instructions. It gains a significant improvement in the critical path.
As shown in Table4.3, the performance of ACARM7 is improved 44.74%
compared to a normalized result from ARM7TDMI and even 22.22% better than ARM7-Korus2005.
Performance Comparison among Three Different Cores Proposed
Performance(MHz) 110 90 76(p.s.1)
Improvement compared
Note p.s.1: Obtained from normalization to 0.18um Table4.3 Performance comparison among 3 different cores
The high-performance of the proposed design has been discussed and analyzed with experimental results this section, and other analyses which are interested by readers will be described in following sections.
4.2.3 Area Comparison
This section discusses the area comparison among the cores. It should pay attention that the area of ACARM7 is in technology of 0.18um and the area of ARM7TDMI is in technology 0.25um. Two results of the area with different
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technologies can not be normalized and compared since design rule check (DRC) with different technologies can not be directed normalized by a single equation.
Nevertheless, the gate-count of ACARM7 is much lower than the one of ARM7-Korus2005 and improves 31.25% compared to ARM7-Korus2005, as shown in Table4.4.
Area/Gate-count Comparison among Three Different Cores
Proposed Core
Table4.4 Area/Gate-count comparison among 3 different cores
The gate-count comparison between the proposed design ACARM7 and ARM7-Korus2005 shows that the core size of the former is much smaller for 2 primary reasons. The first is that no Thumb instruction implementation strategy and the second is that more design considerations are taken into account. The small area/gate-count is also one reason for low-power designs and is what designers and users want to see; On the other hand, power comparison will be analyzed in next section.
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4.2.4 Power Comparison
This section describes power comparisons among the cores above and the power of ARM7TDMI should be normalized to 0.18um technology first by an equation come from P=CV2 and listed below:
0.78 X (
As can be seen in the Table4.5, the power of ARM7TDMI is normalized to 0.404mW after normalization. However, it is still higher than 0.17mW of ACARM7 but lower than 1mW of ARM7-Korus2005. An amazing thing occurs that the power improvement of ACARM7 compared to the normalized power of ARM7TDMI is 57.9% better and is 83% better compared to ARM7-Korus2005.
Power Comparison among Three Different Cores
Proposed Core
Note p.s.1: Obtained from normalization to 0.18um Table4.5 Power comparison among 3 different cores
The proposed design has a characteristic of ultra low-power for many reasons and almost the same with the reasons discussed in Section 4.2.2; in fact, a right implementation strategy with no Thumb instructions, a better choice of high quality
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IP like Fong-adder and Ling-multiplier, and more design consideration taken into account brings such a good performance of the proposed design. On the other hand, Power-Delay-Product (PDP) is also provided in Table4.6. The table still shows the PDP of ACARM7 is 70.7% lower compared to ARM7TDMI and 86% lower compared to ARM7-Korus2005.As a matter of fact, ACARM7 is the only one of the three cores which can look after both sides inclusive of low-power consumption and high-performance.
Power-Delay-Product Comparison among Three Different Cores
Proposed Core
Note p.s.1: Obtained from normalization to 0.18um Table4.6 Power-Delay-Product comparison among 3 different cores
4.2.5 Other Characteristics
Considering of other characteristics of the Table4.2, DFT (Design for Testability) is supported by ACARM7 since chips might fail to work due to manufacture problem; as a result, additional test circuit shall be added such as scan circuit and built-in self test (BIST) circuit.
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ACARM7 is supported a characteristic of cycle-accurate verified by a behavior systemC model and will be discussed in Chapter 5.