We run the SSN simulation to verify the decap combination for voltage fluctua-tion reducfluctua-tion, and the results are shown in Table 5.4, Figure 5.4, and Figure 5.5. We
is no other noise, the PDN system without decap is stable. However, besides the operation frequency, there are still many noise occurred anywhere unexpectedly. To prevent the unexpected noise from causing the PDN system unstable, we should be conservative and make the entire frequency range meet the target impedance.
From viewpoint of chip-package-PCB co-design, we should not just care the impedance at operation frequency, but mind the entire frequency range the unex-pected noise would occur. Although using both the decap combinations selected by rules of thumb and our program could maintain the PDN system within the spec-ification 300mV at operation frequency, as Figure 5.4(a) shows. The whole PDN system includes chip, package, PCB, and VRM, and the unexpected noise exists in low, middle, and high frequency. There might be unexpected noise in low, middle, and high frequency. Therefore, we measure the voltage fluctuation when there is a noise coming from PCB or chip at 90MHz, as Figure 5.4(b) shows. The manual selection is not effective to suppress the noise, and our result could still keep the PDN system voltage fluctuation under 300mV. Table 5.4 shows the improvement is 46.69%.
Another problem we should take care is that sometimes the performance of PDN with decaps is worse than PDN without decaps since the anti-resonance[25] might occur at the noisy frequency. As Figure 5.5(a) and Figure 5.5(b) show, the decaps selected by rules of thumb cause the voltage fluctuation larger than the original design without decaps. Table 5.4 shows the improvements of decaps selected by manual are -54.7% in Case-2 and -37.4% in Case-3. Therefore, choosing decap should consider its own characteristic rather than rules by thumb, or we may obtain the PDN system worse than the original design.
Table 5.4 shows the improvement of PDN system with and without decap op-timization, and we could observe that with decap optimization by our program, the voltage fluctuation could be improved obviously and this could make the design
more robust at the same cost and avoid over-design.
Table 5.4: Peak-to-peak voltage fluctuation comparison Case
Case-1 (2-port) 800MHz 338mV 253mV 247mV
Case-1 (2-port) 90MHz 374mV 330mV 278mV
Case-2 (5-port) 100MHz 724mV 1120mV 386mV
Case-3 (16-port) 200MHz 270mV 371mV 179mV
Case
(a)
(b)
(c)
Figure 5.1: Comparison of decap combination cost chosen by PDC-PSO, PSO and SA. We run each algorithm 50 times and record its result. T-I means the target impedance. (a) is the algorithm comparison of Case-1. (b) is the algorithm com-parison of Case-2. (c) is the algorithm comcom-parison of Case-3.
(a)
(b)
(c)
Figure 5.2: Comparison of PDC-PSO, PSO and SA in lowering PDN impedance. We
(a)
(b)
(c)
Figure 5.3: All cases frequency spectrum. (a) is the Case-1 comparison of original and optimal decap combination in frequency domain. (b) for Case-2. (c) for Case-3.
(a)
(b)
Figure 5.4: 1 time domain spectrum. P-P means peak-to-peak. (a) is the Case-1 time-domain comparison of original and optimal decap combination in 800MHz.
(b) is the Case-1 time-domain comparison of original and optimal decap combination in 90MHz.
(a)
(b)
Figure 5.5: Case-2 and Case-3 time domain spectrum. P-P means peak-to-peak. (a) is the Case-2 time-domain comparison of original and optimal decap combination in 100MHz. (b) is the Case-3 time-domain comparison of original and optimal decap combination in 200MHz.
Chapter 6 Conclusions
A well-designed PDN is essential for high speed system. To maintain the power integrity, adding decaps is an effective way. Since the more decaps would cost more money and area, how to choose decaps becomes a critical issue. In this thesis, we introduce an efficient algorithm named “PDC-PSO” to optimize the type and loca-tion of decaps automatically. The results show that, compared to the decaps chosen by rules of thumb, our algorithm could effectively shrink the voltage fluctuation at pads on chip within the tolerable range at the same or lower price in a relatively short execution time.
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