To reduce the opportunity of IC failure by electrostatic discharge (ESD), the ESD protection circuit provided by STC I/O PAD is utilized to guarantee the low impedance ESD path between any I/O pads of the chip. As shown in Figure 3.11, I/O ports are protected by NMOS and PMOS with gates connected to ground and power supply respectively [17]. In normal operation, there is no leakage current since the
40
transistors are turned off by power rail. However, when the circuits are under ESD, forward biased parasitic diodes with RC triggered power rail ESD clamp circuit provide low impedance ESD current paths.
VDD
GND Internal
Circuit I/O
Parasitic diode RC-triggered power rail ESD clamp circuitry
M1
M2
M4
M5 M3
M6 R
D1
D2
Figure 3.11: The circuit design of ESD protection
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Chapter 4 MEMS and ASIC Co-Simulation
In this section, we explore the model for co-simulation and monolithic circuits with one axial accelerometer of simulation results. It’s so important that the computer aided design flow for MEMS and IC integration is used to co-simulate. The difficulty is that the multi-layer structure of CMOS MEMS sensors are either modeled with highly simplified lumped-mass models, or simulated by accurate, but very time-consuming, finite element analysis (FEA). Therefore, a newly proposed approach provides the accuracy of FEA and connection with circuits for co-simulation by MEMS+ with parametric computation to save computational time.
4.1 The Introduction of MEMS+
4.1.1 The Flow of MEMS and ASIC Co-Simulation
In order to reach high integration of integrated circuits with sensors, the relations between simulation and measurement results must be highly accurate. As shown in Figure 4.1, the design flow for MEMS design and co-simulation is illustrated and the tool is divided into four parts, material data base, process editor, innovator, and MEMS+ scene 3D. Material data base and process editor are the same as the parts on CoventorWare. We set material parameters and process on material data base and process editor, respectively. Like the library of circuit design, the component library of MEMS+ such as rigid plate and suspensions is used to construct the sensors in
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Design a 3D parameterized MEMS modeling
Create a Cadence netlist and symbol Animate the motion of
the MEMS device Import to MEMS
plus Scene3D
Figure 4.1: The flow of co-simulation
innovator. Contrast with finite element analysis by CoventorWare, MEMS+ generates the physical behavior model (PBM) more quickly and easily and it is absolutely designed for co-simulation with IC design. The PBM generated from MEMS+ is imported to Cadence and then it generates a Cadence netlist and symbol for sensor performances such as resonant frequency and mechanical sensitivity. After simulating for characteristics of PBM at DC and AC analyses, the results could be imported back to MEMS+ for animating the sensors. The PBM symbol is used to connect with circuits for co-simulation. The parameters of the symbol could be set as variables and its values could be changed before co-simulation. The voltage values in Cadence are
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used to on behalf of the mechanical force. According to the final co-simulation results, the final integration system is determined to be worthy to implement it.
4.1.2 Auto-Generated Layout of One Axial Accelerometer
Comparing with the artificial layout of the accelerometer by layout tool such as Virtuoso and Laker, the auto-generated layout is error-free as long as ensuring each component connecting others on MEMS+. In order to produce the auto-generated layout, the gds numbers of layers need to be set in the process editor window on MEMS+ as shown in Figure 4.2. The auto-generated layout from Metal1 to Metal6 layers is shown in Figure 4.3 (a) compared with Figure 2.8. Assisted by other layout tool, the auto-generated layout is added to other layers for MEMS process as shown in Figure 4.3 (b).
Figure 4.2: The process editor window
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(a) (b)
Figure 4.3: (a) The auto-generated layout of the accelerometer, and (b) Adding RLS and PAD layers to the auto-generated layout
4.2 Co-Simulation Model
Three co-simulation models of MEMS sensors will be described in this section.
Two of them are generated from VerilogA in Cadence. The other is generated from MEMS+ and imported to Cadence.
4.2.1 Co-Simulation with Lumped-Parameter Macro Model
According to the second order motion equation of (2.1), the principle of co-simulation models is the equivalent relationship between mechanical structures and circuits. The equation (2.1) is equivalent to
L
dd22qt+ R
dqdt+
C1q = V
(4.1) where L, R, C, q, and V are inductance, resistance, capacitance, coulomb and voltage, respectively. The following simplifications listed in Table 4.1 are used to get the lumped-parameter macro-model of the accelerometer through the second-order45
motion equation. As shown in Figure 4.4 (a), the proof mass m is equal to L, the damping coefficient b is equal to R, and the spring constant k is equal to 1/C. Others such as g1, g2, and g3 are used for co-simulation. Cs and d are the initial capacitance value and the distance of gap between a stator and a rotor, respectively. The equivalent capacitors of equations are given as
Cupe =
Cs∗dd−∆d
=
Cs1−g3∗Vs (4.2)
Cdne =
Cs∗dd+∆d
=
Cs1+g3∗Vs (4.3) where Cupe and Cdne are the macro model symbol of the top and bottom capacitance plates, respectively. Vs is the force in the voltage form of Cadence. The equivalent capacitors in the circuit form shown in Figure 4.4 (b) are connect to the C to T circuit for RC charging and discharging. The principle of the equivalent capacitor is simplified to first order only by the displacement of the variation (Δd) from Hooke's
law. Therefore, the simplified accelerometer model of the simulation time is faster than the PBM, but the available data are fewer than the PBM.
Table 4.1: Mechanical parameters transfer to electronic parameters Mechanical Electrical Value
m L 8.44e-9
b R 2.06e-6
1/k C 0.68
g1 9.8*m 8.271e-8 g2 Cs/2d 5.695e-8
g3 C/d 1.7e+5
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m b
F=ma 1/k
+ Vs
Cupe = Cdne =
Cs*d d-△d Cs*d d+△d
Figure 4.4: (a) Equivalent lumped-parameter macro-model circuit of the accelerometer, and (b) The equivalent capacitors of the macro model
4.2.2 Co-Simulation with Linear Model
Another co-simulation model with the linear characteristic is designed in VerilogA form. In order to know what the PBM is, the linear model is generated to make sure that if it is similar to PBM or lumped-parameter macro-model in the part of the sensing capacitance. The capacitance value of the equivalent Cupl and Cdnl are proportional to the sensitivity of the accelerometer as shown in Figure 4.5. The Cupl and Cdnl of the equations are given as
Cupl = Cs + sen ∗ V (4.4) Cdnl = Cs − sen ∗ V (4.5) The sen and V are the capacitance sensitivity of the accelerometer and the force in the voltage form of circuit, respectively. One volt is used to simulate one gravity in the two VerilogA models, lumped-parameter macro model and linear model. These are the same parameters in Table 5.1 for the linear model except the equivalent capacitors, the variation of the displacement and the linearity.
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Cupl = Cdnl =
Cs+sen*V Cs-sen*V
Figure 4.5: The equivalent capacitors of the linear model
4.2.3 Co-Simulation with Physical Behavior Model
The MEMS+ generates the PBM symbol for co-simulation in Cadence as shown in Figure 4.6. The sensors are designed from MEMS+ component library such as rigid plates and suspensions by MEMS+ and the feature is that the width and length of components could be parameterized. The parameterized sensors are imported to Cadence which creates physical behavior model (PBM) for mechanical characteristics and co-simulation. The mechanical characteristics of the accelerometer about Table 2.3 are simulated in Cadence design environment using Spectre simulator. The model is divided into two parts, input and output nodes. Acceleration and angular velocity of stimulating sources in circuits form as shown in Table 4.2 could drive sensor models in the circuit simulation platform. Variables at the input node signify that the length and width of sensors could be changed before running the simulation. The function of electrical connectors is used to connect to circuits such as C to V or pre-amplifier to simulate the action of capacitances for co-simulation. The mechanical features of
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sensors as shown in Table 4.3 are simulated from mechanical connectors. Initial capacitance and capacitance sensitivity between any two capacitor plates are simulated from the output node of capacitance.
Input
Figure 4.6: The symbol of physical behavior model Table 4.2: Input node of PBM
Input Unit Scale Factor Acceleration 1 m/s^2=1e-6 V
Angular
Table 4.3: Output node of PBM
Output Feature
Electrical
Connectors For connecting to circuits Mechanical
Connectors
Displacement、Resonant frequency、
Rotation Capacitance Values Initial capacitance、
Sensitivity
4.2.4 Comparison
In this section, the above-mentioned co-simulation models will be compared at the situation which C to D circuits are connected. The sensor structure is simulated by
49
finite element analysis (FEA) to obtain the sensor characteristics and fed parameters into simplified macro model and linear model on MEMS designs. Based on connecting with capacitance to pulse-width circuit in the simulation time part, the macro model and linear model are the second order due to equation (4.1), and simulation time of PBM is longer than the other two. Then 9bits counter is added to pulse-width circuit to form C-to-D circuit and the simulation time of PBM is still longer than the other two. The simulation time between lumped-parameter macro model and linear model is almost the same due to the only dissimilarity in equivalent sensing capacitance model. According to the two row results of the simulation time, the situation of PBM with more circuits will take more simulation time than the two others. And the difference of the relative time with adding more circuits will be longer.
In the available data part, macro model and linear model are only used to show the results of equivalent sensing capacitance on Cadence, but PBM is used to both present the results of equivalent sensing capacitance and mechanical features like Table 4.3.
PBM is like a block box that we don’t know its principle. Therefore, based on the co-simulation with capacitance to pulse-width circuit at -5g to 5g and transient analysis in the simulation result part, Figure 4.7 is showed that PBM is similar to the linear model in the part of equivalent sensing capacitance with circuit. The pulse-width steps of macro model in simulation result are bigger than the linear model
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and PBM, and it will result in that the sampling rate and power consumption are smaller than the others. Due to the aided design and co-simulation of MEMS+, we use PBM to finish the design. However, the three models are still compared with the measurement results.
Table 4.4: The comparisons of three co-simulation models Lumped-Parameter
Macro Model Linear model PBM
Simulation time (Connecting with
pulse-width circuit)
1.015 (Unit: second/period) 0.961 12.9
Simulation time (Connecting with
C-to-D circuit)
773 (Unit: second/period) 769 3600
Available data Sensing capacitance sensing capacitance
Showed in Table 4.3
Simulation result Green triangle in Figure 4.7 Red square in Figure 4.7
Blue diamond in
Figure 4.7
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Figure 4.7: The pre-simulation of the three models with capacitance to pulse-width
4.3 System Simulation
The proposed circuit with one axial accelerometer is simulated in Cadence design environment using Spectre simulator and operated with supply voltage 1.8V.
The PBM is used to the co-simulation with circuits in Cadence. As shown in Figure 4.8, there are seven simulation results on typical-typical, slow-slow, fast-fast, 0 and 50 degrees Celsius, VDD of 90% and 110% conditions. Each result just changes one condition and fixes the six others. One set of code is equivalent to one set of time value in -5g to 5g. At the sensing range, the resolution reaches to 20ns/1bit by C-to-D circuit. The system simulation results of C-to-D circuit with one axial accelerometer are shown in Table 4.5.
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Figure 4.8: The post-layout simulation of the pulse-width in C to D circuit with accelerometer
Table 4.5: Specifications of C-to-D circuit with the accelerometer Unit Value
Sensitivity us/pF 6.94 Dynamic range fF 441.2~470
Resolution ns/1bit 20
Sampling Rate MHz 50
Power Consumption mW 5.47
5.500 6.000 6.500 7.000 7.500 8.000 8.500
440.00 445.00 450.00 455.00 460.00 465.00 470.00
The simulation of the pulse width by 9bits
Post_TT Post_SS Post_FF Post_0度 Post_50度 Post_1.62V Post_1.98V
fF
us
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Chapter 5 Measurement
5.1 Measurement Results of T18-101A
The monolithic accelerometer with C-to-Pulse-Width circuit has been implemented in T18-101A. The designed core of T18-101A is focused on the sensitivity of C-to-PW circuits with the fixed capacitance value, 100fF to 1100fF, and the initial capacitance value of the accelerometer compared with the value of the co-simulation. The results of measurement and co-simulation are shown in Figure 5.1, and the measurement results of chip1~8 are averaged to form the square symbol curve in Figure 5.2. We can find that there is one unusual thing in the measurement from Figure 5.2. The initial capacitance value of the accelerometer which is with star mark
Figure 5.1: The measurement of chip1~8 of T18-101A
4.2 4
100 200 300 400 500 600 700 800 900 1000 1100
Chip1
The measurement of T18-101A
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Figure 5.2: The comparison of T18-101A between simulation and measurement the value is about 1800fF compared with 455.6fF of the simulation. There are two possible reasons for the difference, and one is that effect of parasitic capacitance results in the enlarged pulse width. The effective sensing capacitance, Ceff, is dependent on the parasitic capacitance seen by the sensing node V2 of Figure 3.2. We can express Ceff as follows:
Ceff≈ CPCB+ CMOS+ Cx (5.1) where CMOS is the capacitance from MOS devices, Cx is the sensing capacitance, and CPCB is the off-chip PCB parasitic capacitance seen by the sensing node V2. The linearity between the pulse-width and sensing capacitance is not affected by the
parasitic capacitance. It only introduces a fixed offset proportional to CPCB and CMOS in the pulse-width. The other possible reason is that the accelerometer is unreleased
and unsuspended to result in parasitic capacitance of silicon substrate to enlarge the 4.4us/pF
4.5us/pF
4.4us/pF Offset: 748fF
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pulse-width compared with the simulation. The reason is also that why we took SEM and FIB pictures in the cross-section of the sensor and find a series of issue of the sensor.
5.2 Measurement Results of T18-101B
The monolithic accelerometer with C-to-D circuit has been implemented by TSMC 0.18um 1P6M CMOS mixed-signal process and APM MEMS process in T18-101B. The layout of the accelerometer with C-to-D circuit on a single chip is shown in Figure 5.3 and its size is 1343um*1419um. The accelerometer takes an area of 793um*812.5um. The die photo of the integrated chip by optical microscope is shown in Figure 5.4. The chip connects to the circuit board through bonding wires as shown in Figure 5.5.
Accelerometer
C-to-D
Figure 5.3: The layout of the integrated chip
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MEMS motion analyzer (MMA) of CIC is used to test the movement and resonant frequency of sensors as shown in Figure 5.6, and the setting of the measurement is set to sweep from 1kHz to 4kHz. The measurement results of the Chip1, 2, and 6 are 2.5kHz as shown in Figure 5.7 compared with 2.19kHz of the simulation.
Measuring instruments used in the measurement include a shaker with vibration control system, a reference accelerometer, power supplies, a function generator, a
Accelerometer
C-to-D circuit
Figure 5.4: The die photo of the chip
Bonding
Figure 5.5: Photos of bonding board and bonding wire
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Figure 5.6: MEMS Motion Analyzer
logic analyzer, and other supporting instruments. The function of the reference accelerometer is used to detect the current force value. The reference accelerometer PCB 352C44 is fixed on the shaker with a sensitivity of 100mV/g. The sinusoidal reference acceleration input, with 100Hz and 1-gravity to 5-gravity, are shown in Figure 5.8 to 5.12. The logic analyzer is used to catch the data of 9bits counter in the range of 0 to 25m second about four periods, and the bits number is related to the gravity of the moment when the reference sinusoidal acceleration is at the peak value.
Then the bits number of the peak value is averaged in the peak of four periods.
The chip under test is wire bonded on the package and mounted on the experimental circuit board for measurement. LDS shaker generates the input acceleration to test the initial capacitance and the capacitance sensitivity. The major instruments used in the measurement are summarized in Table 5.1. The setup of the
58
measurement environment is shown in Figure 5.13 for testing the chip. There are two single-axis accelerometers on LDS shaker. One is the reference accelerometer with orange clay for fix the reference one, and the other is the designed accelerometer on the test board. With supply voltage VDD=1.8V, it dissipates a 428.9uA of current and results in a 772uW of static power consumption.
Table 5.1: Instruments used in the measurement
Instrument Model Key Features
Shaker LDS 406-PA100E
Input acceleration range:
±10g Frequency range:
5Hz-9kHz Vibration control
system LDS Laser USB Signal analysis
Spectrum analysis Reference
accelerometer PCB 352C44 Acceleration:±5g
Sensitivity: 100mV/g
Power supply Agilent E3632A Output: 15V/7A
Function generator Tabor Electronics
WW2572A Square wave:50MHz
Logic analyzer Agilent 16902A 4 pods, 16channels/pod Fixture Local customization Length x Width x Height:
11x6.5x9.5
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Figure 5.7: The measurement results of resonant frequency of the accelerometer
0 0.004 0.008 0.012 0.016 0.020 0.024 0.028 0.032 0.036 0.040
0
Figure 5.8: 1G, 100Hz sinusoidal reference acceleration input
0
0 0.004 0.008 0.012 0.016 0.020 0.024 0.028 0.032 0.036 0.040
Figure 5.9: 2G, 100Hz sinusoidal reference acceleration input
0
1000 1500 2000 2500 3000 3500 4000
Chip1
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0 0.004 0.008 0.012 0.016 0.020 0.024 0.028 0.032 0.036 0.040
Figure 5.10: 3G, 100Hz sinusoidal reference acceleration input
0
0 0.004 0.008 0.012 0.016 0.020 0.024 0.028 0.032 0.036 0.040
Figure 5.11: 4G, 100Hz sinusoidal reference acceleration input
0
0 0.004 0.008 0.012 0.016 0.020 0.024 0.028 0.032 0.036 0.040
Figure 5.12: 5G, 100Hz sinusoidal reference acceleration input
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Power Supply Function Generator
Logic Analyzer
Reference Sensor
Chip on board
LDS Shaker LDS Power Amplifier
Board
Chip Fixture
Figure 5.13: Photos of instruments
The chip5 is destroyed due to the bonding. With -5 to 5 acceleration of gravity of input from LDS shaker, the measurement results of gravity to Time (g to T) of other chips are shown in Figure 5.14, and it shows that chip1, 2, and 6 are close to increase linearly and more linear than chip3 and 4. Chip1, 2, and 6 are averaged to form the AVG curve as shown in Figure 5.14. The measurement results compared with the simulation are shown in Figure 5.15. The results are divided into two parts, gravity to capacitance (g to C) and g to T. The part of g to T is measured from the testing environment, and the other part of g to C is derivate from both g to T of measurement and capacitance to time (C to T) of the simulation. It shows higher capacitance sensitivity and lower linear characteristic compared with the simulation. The measurement results show that the capacitance range is 640fF to 890fF with -5 to 5 gravity and the capacitance sensitivity of the black linear trend line is 23.02fF/g. All chips of the measurement results are shown in Table 5.2 compared with the simulation.
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Because the curves of measurement results show the non-linear feature, the sensitivity of capacitance and g to T are simplified from linear trend line of each chip. Obviously, the sensitivity and dynamic range of the measurement results are bigger than the simulation. The possible reasons are that the parasitic capacitance and offset of circuits are made to enlarge the pulse-width and digital bits. The overall conversion relation is given as
g → C → PW → D (5.2) where g is gravity, C is the measured capacitance, PW is pulse-width, and D is the digital bit. There is some capacitance offset in C-to-PW circuit, but the sensitivity is accurate from the measurement results of T18-101A. The measured D values are directly transferred to PW values. Therefore, there are two possible reasons. One is the accuracy of the co-simulation model from MEMS+, and the other is the added D values due to the noise. The resolution of PW could be introduced the noise, but the design is based on one bit for one gravity from MEMS+ because the capacitance range between simulation and measurement is still verified.
Comparing with [7], the sensing capacitance range of this design is smaller 10 times as shown in Table 5.3. The sensor with circuits on single chip and fully digital output signal of the features are over than others. The circuit is designed to use the 9bits counter and 50MHz sampling rate to readout the fully digital, so the power
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consumption is over than others.
Figure 5.14: The measurement results of g to T of chips
Figure 5.14: The measurement results of g to T of chips