Experimental Results

For presenting the performance of the prototype based on the proposed topology, the circuit of Fig. 2.6(b) and (c) has been built and tested in the specifications described in Section 3.4.

The parameters of the critical components are given in Table 3.5. Because the input current

i

_in= i_LB of the proposed converter is pulsating when L_B operates in DCM, the EMI level would be above the limits of standard such as FCC or CISPR. Hence, an input filter which low input displacement angle between input voltage and current, minimum interaction with the con-verter and system stability is designed to attenuate EMI to meet regulatory specifications and get smooth waveform of line input current i_ac in Fig. 3.8 and 10(a). The detailed design and analysis about input filter could be referred to [18] and [19]. The key waveforms at Vac=85 V_rms/P_out=60 W, V_ac=265 V_rms/P_out=60 W, and V_ac=265 V_rms/P_out=20 W are presented in Fig.

3.8, and the switching current waveforms for M1 mode and M2 mode at Vac=130 V_rms/R_L=60.24 are presented in Fig. 3.9. As can be seen, the shapes of line input current i_ac are approaching to the average input currents shown in Fig. 3.2. The measured key waveforms at the worst condition (V_ac=85 V_rms and P_out=80 W) are shown in Fig. 3.10(a) and the power factor is 0.91. Although the line input current is distorted due to the SCM operation of LB, its harmonic contents still comply with the class D limits as shown in Fig. 3.10(b) and the total harmonic distortion is 45.5%. Fig. 3.11 shows the measured bulk capacitor voltage versus load under line variations. The maximum bulk capacitor voltage is 415.4 V, which is below the commercial size 450 V and occurs at Vac=265 Vrms with Pout=20 W. Fig. 3.12 shows measured power factor versus load under line variations. It can be seen that the lowest power factor is 0.91 and occurs at the worst condition. The power factors at most conditions are above 0.95 and some even reach 0.99. As described in Section 3.3 and C, L_B tends to operate in CCM as input voltage decreases and load increases, and the worst DCM condition for LB is

Ω

mode (SCM) when Pout is greater or equal to 60 W. Consequently, iac is distorted and PF de-grades as can be seen V_ac=85 V_rms curve in Fig. 3.12. Fig. 3.13 shows efficiency versus load under line variations. The efficiency is greater than 80% in most operating range, and the maximum value is 85.8% at V_ac=130 V_rms with P_out=60 W.

Table 3.5 Parameters of critical components

L

B 35

μ

H

T1

L

M1=145

μ

H; n1=1.6 T2

L

M2=1.4 mH; n2=1.8

S K2968

C

B 470

μ

F/450 V

C

O 220

μ

F/100 V

V

_CB

V

_O

i

_ac

v

_ac

5 ms/div V

_CB

(50V/div), V

_O

(50V/div),

v

_ac

(50V/div), i

_ac

(1A/div)

(a)

5 ms/div v

_ac

(100V/div)

i

_ac

(200mA/div)

(b)

5 ms/div v

_ac

(100V/div)

i

_ac

(100mA/div)

(c)

Fig. 3.8 Measured line voltage, bulk capacitor voltage, line current, output voltage:

i _DO1 (0.5A/div)

v _O (2V/div)

2 μs/div i _DO2 (1A/div)

(a)

i _DO1 (1A/div)

i _DO2 (1A/div)

v _O (2V/div)

5 μs/div

(b)

Fig. 3.9 Measured switching current waveforms: (a) M₁ mode and (b) M₂ mode at Vac=130 Vrms, RL=60.24

Ω

.

V

_CB

(50V/div), V

_O

(50V/div), v

_ac

(50V/div), i

_ac

(2A/div)

V

_CB

V

_O

i

_ac

v

_ac

5 ms/div

(a)

Harmonic Content and Class D Limits

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

3 5 7 9 11 13 15 17

Harmonic Number

mA /W

Measurement Class D

(b)

Fig. 3.10 (a) Line voltage and line current measured at the worst condition (Vac=85 Vrms and

P

_out=80 W) and (b) harmonic content and class D limits.

10 20 30 40 50 60 70 80 90 100

150 200 250 300 350 400

450 V_CB (V) Bulk Capacitor Voltage

P_out (W) V_ac=265 V_rms

V_ac=220 V_rms

V_ac=175 V_rms

V_ac=130 V_rms

V_ac=85 V_rms

Fig. 3.11 Measured bulk capacitor voltage versus load under line variations.

10 20 30 40 50 60 70 80 90

0.9 0.91 0.92 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1

Power Factor

v_ac=265 V_rms v_ac=220 V_rms v_ac=175 V_rms v_ac=130 V_rms v_ac= 85 V_rms

P_out (W)

Fig. 3.12 Measured power factor versus load under line variations.

10 20 30 40 50 60 70 80 90

78 80 82 84 86

88

Efficiency (%)

P_out (W)

v_ac=265 V_rms v_ac=220 V_rms v_ac=170 V_rms v_ac=130 V_rms v_ac=85 V_rms

Fig. 3.13 Measured efficiency versus load under line variations.

CHAPTER 4

C ONTROLLER D ESIGN FOR A S INGLE -S WITCH P ARALLEL

B OOST -F LYBACK -F LYBACK C ONVERTER

The electronic dc loads are wide spread interfacing on the utility system via AC/DC con-verters. Conventional two-stage AC/DC converter uses the power factor stage to obtain sinu-soidal input current and a DC/DC stage to regulate output voltage. The DC/DC stage needs a fast voltage control loop, and the power factor correction (PFC) stage requires three intercon-nected control loops [24]: a wide bandwidth loop for shaping the input current, a slower loop for output voltage regulation, and a low-pass-filtered line-voltage RMS loop to ensure in-put-output power balance. This approach can get nearly unity power factor, yet has the draw-back of complex circuit and high cost. For the purpose of simplicity and cost down, the two processing stages are integrated to the single stage (S²) AC/DC converters, such as boost in-tegrated/flyback rectifier/energy storage/dc-to-dc converter (BIFRED) [25], boost input cur-rent shaper [4, 26], parallel converter [13, 21, 27] were also presented. In those designs, only one output feedback controller is needed and the input current shaping is automatically achieved. Usually, small signal transfer function and bode plots were employed for compen-sator design [28]. Unlike traditional dc-to-dc converters, variations in the line voltage and duty ratio cannot be ignored in the AC/DC power factor correction converters modeling. For the S² converters [4, 25-26] that integrate a DCM boost inductor with a dc-to-dc stage, the duty ratio has to be held relatively constant to regulate output voltage and improve power factor. The small signal model of such converter with constant duty can be built with double averaging method [29] or Fourier series substitution [10], and verified by frequency response measurement technique [31]. However, for parallel converter, which allows partial power to be processed only once or transfers partial power directly. They have duty ratio varied with

cycle [13, 21]. Hence, as described in [32] the small signal transfer function of the converter with variable duty ratio cannot be validated with frequency response instrument, because the operating points are not constant. Fortunately, the problems of operating point changing and different operation modes can be solved by large signal method [32] or switched transformer average model [33]. Nevertheless, the controller design for parallel converter operating under universal voltage and load variation is seldom to see in publishing literatures. If the control loop features are poor, not only additional distortion might appear in the input current but also higher output voltage ripple would be induced.

The single-stage-single-switch (S⁴) parallel boost-flyback-flyback converter mentioned in chapter 2 and 3 had been presented by [34] and is of parallel structure for universal usage with high efficiency. The parallel converter operates as other parallel converters have variable duty ratio and two operation modes. Therefore, this dissertation proposes the small signal modeling and the controller design for S⁴ parallel boost-flyback-flyback converter. First, the nonlinear large signal models of two operation modes are described according to the operation principle.

By linearizing the large signal models, the small-signal models are developed as the state space equations. From the equations, the uncertainty of transfer function caused by the changing of operation points is investigated. To overcome the uncertainty problem, an opti-cally isolated feedback compensator for current mode control is proposed. The compensator is designed according to the transfer function at the boundary of modes and assures small steady state error, fast rise time, and heavily damping within operation range. The dynamic model and designed controller of parallel boost-flyback converter are demonstrated by simulation and experiment.

D

_O1

R

_L

Fig 4.1 Schematic diagram of S⁴ parallel boost-flyback-flyback converter with optocoupler feedback current mode controller.

Fig. 4.2 Illustrated waveforms within one switching period: (a) for DCM-DCM boost-flyback semi-stage + CCM flyback DC/DC semi-stage (M1 mode); (b) for DCM-DCM boost-flyback

semi-stage + DCM flyback DC/DC semi-stage DCM (M2 mode)

Duty ratio

d=D_m1

|v_ac| M₁

π 2

Average Magnetizing Current of T₁ and T₂

<i_LM1(θ )> <i_LM2(θ )>

M₁

CCM DCM

π

(a)

Duty ratio

|v_ac|

d=d_m2(θ )

π 2π

M₂ M₁ M₂

M₁ M₁

d=D_m1 ^d=Dm1

d=D_m1

d=d_m2(θ )

<i_LM1(θ )> <i_LM2(θ )>

Average Magnetizing Current of T₁ and T₂

DCM

DCM CCM

CCM CCM

DCM DCM

DCM

DCM DCM

θ_Τ π−θ_Τ π+θ_Τ 2π−θ_Τ

(b)

<i_LM1(θ )> <i_LM2(θ )>

π 2π

d=d_m2(θ )

M₂

|v_ac| Duty ratio

Average Magnetizing Current of T₁ and T₂

DCM

DCM

M₂

(c)

Fig. 4.3 Operation waveforms in a line cycle: (a) case I (M1 mode only), (b) case II (both M1

and M₂ modes), and (c) case III (M₂ mode only).

4.1 Small Signal Modeling

In this section, both the small-signal modeling for S⁴ parallel boost-flyback-flyback con-verter and current mode control with optocoupler feedback are developed for controller design.

The boost-flyback-flyback converter with optocoupler feedback current mode controller is plotted in Fig. 4.1. The waveforms within a switching period for the waveforms for M1 and M₂ modes are shown in Fig. 4.2(a) and (b), respectively. The major current waveforms and the corresponding duty ratio waveforms of three combination cases are depicted and shown in Fig.

4.3.

4.1.1 M

₁

Mode

It can be seen from Fig. 4.1 that there are five energy storage elements LB, LM1, LM2, CB and

C

_O in the converter. For M₁ mode, both L_B and L_M1 operate in DCM, and their initial and final inductor currents vanish in each switching period TS. Thus, these inductor currents should not be selected as state variables. Whereas L_M2 operates in CCM, and thus, only v_CB, v_CO, and fly-back DC/DC transformer magnetizing current iLM2 are chosen as the state variables in the fol-lowing small-signal modeling.

Based on the definition (2.1), the average state variable description of the converter is

( ) ⁱ ( ) ^t

dt t v

C

_B

d

^CB

=

_CB (4.1a)

( ) ⁱ ( ) ^t

dt t v

C

_O

d

^CO

=

_CO (4.1b)

( ) ^v ( ) ^t

dt t i

L

_M2

d

^LM2

=

_LM2 . (4.1c) Moreover, in DCM, the inductor voltage averaged over a switching period is zero and inde-pendent of duty ratio. Hence, two constraints are given by

( )

1

( ) ⁰

1

1

= v t =

dt t i

L

_M

d

^LM _LM (4.2a)

( ) = v ( ) t = ⁰

dt t i

L

_B

d

^LB _LB (4.2b)

and the output equation is expressed as

( ) ^{t v} ( ) ^t

v

_O

=

_CO (4.3) From the waveforms in Fig. 4.3, the averaged variables in (4.1a)-(4.2b) can be written as

( ) ^{t i d} ( ^{i i i} ) ^d

Substituting (4.4d) and (4.4e) into constraint (4.2a) and (4.2b) yields

( ) ( )

Substituting (4.5a)-(4.5c) and (4.6a)-(4.6b) into (4.4a) and (4.4b) yields

( ) ( )

(

1

)

²

Substituting (4.4c) and (4.7a)-(4.8b) into (4.1a)-(4.1c) yields

( ) ( )

In (4.9a) and (4.9c)

C

_Bis sufficiently large,

v

_CB can be considered as constant . Besides, a dynamic equation linearized around the operating point is derived as follows. Small perturba-tions: intro-duced into (4.9a)-(4.9c). Thus, the linearized small-signal model is given by

[ ] ^x [ ] [ ] [ ] ^{A x B v}

in

[ ] [ ] ^{B i}

O

^{B d}

where the parameters are expressed as

{ } x ~ [ ~ i

LM

v ~

CO

]

^T

is system input, which is manipulated by the controller,

v~

_inand

~ i

_O

stand for the exogenous disturbances, which are not manipulated by the

controller, and

~ y

is the sensed or measured output. Hence, the following five transfer func-tions for M₁ mode can be derived from (4.10) and (4.11) by Laplace transformation: the open loop audio susceptibility

^G

VV

^v

O

( ) ( ) ^{s v}

in

^s

~

= ~

, the line-to-inductor current transfer func-tion

^G

IV

ⁱ

LM

( ) ( ) ^{s v}

in

^s

With substituting (4.12a)-(4.12b) and (4.13) into (4.1a)-(4.1c), (4.9a)-(4.9c) can be expressed as With (4.13), (4.14a)-(4.14c), parameters in (4.11) can be reduced to

{ } x ~ = [ v ~

CB

v ~

CO

]

^T,

CO (4.15). Furthermore, it can be seen from (4.11) and (4.15) that, the input voltage

( ^t )

V

V

_in

=

_pk

sin ω

_L

⋅

in the model is time-dependent, RL is varied within required range, and D is not fixed in M2 mode. Furthermore, the small-signal modeling of M1 is quite different from that of M₂ mode. These modeling uncertainties would be a challenge to design a compensator with robustness.

4.1.3 Current Mode Controller and Optocoupler Feedback

As mentioned in [35], the current-mode controlled converter possesses the advantages of input voltage feed forward characteristic and easy of making current limiting, and optocoupler is the most popular and widely used for necessary isolation of analog error signal. Hence, the commercially available IC UC3844 associated with TL431 based optically feedback circuit is employed to implement the switching control of parallel boost-flyback-flyback converter as shown in Fig. 4.1.The output voltage signal vO is transferred to UC3844 via TL431 and opto-coupler, the switch current i_S is sensed and fed back to the comparator, then the duty ratio d of control switch S is well controlled.

Its necessary components include TL431, the output voltage error calculation circuit G_EA (RO1, ZC2), the optocoupler, and the compensator of current mode control. The TL431, which consists of voltage reference, amplifier and driver, is designed as a shunt regulator for modu-lating the LED current in response to the feedback voltage error. Then an error voltage is yielded from the optocoupler output, and the current command is further generated from the

compensator AOC, which is implemented using the compensating network (ZC3, ZC4) con-nected externally. Through properly choosing the low pass filter Z_E and the current compensa-tion network according to the power stage dynamic behavior, the excellent current mode con-trol is yielded. The small signal model of the optocoupler feedback circuit is derived with Laplace transformation as follows:

For M₁ mode, the flyback DC/DC semi-stage operates in CCM. With the CCM current mode control model proposed by Ridley [36], and the control voltage is expressed as

v

_C

= V

_C

+ v ~

_C, duty ratio perturbation

d ~

is related to its control perturbation

v~

_C and in-ductor current perturbation 2

~

ig-nored and current mode control modulator gain FM is equal to the on-time slope of the cur-rent-sense waveform S_n, as duty ratio is smaller than 0.5 for UC3844. The small signal block diagram of parallel boost-flyback-flyback converter with optocoupler feedback current mode controller for M₁ mode is shown in Fig. 4.4(a), and the control-to-output transfer function is given as For M₂ mode, the flyback DC/DC semi-stage operates in DCM. According to the DCM cur-rent mode control model [37],

d ~

The small signal block diagram of parallel boost-flyback-flyback converter with optocoupler feedback current mode controller for M₂ mode is shown in Fig. 4.4(b), and the con-trol-to-output transfer function is given as

( ) ^{s F G} ( ) ^s

G

_VC

=

_{M VD} . (4.19) The output sensing feedback transfer function is given by

( ) ( )

The transfer function of compensator and optocoupler is given by

( ) ( )

The output-to-control transfer function can be expressed as

( ) ( ) A ( ) s ( G ( ) s

The loop gain is derived as

( ) ( ) ^{s A s} ( ^G ( ) ^s )

where

G

_C

( ) s

is the compensation transfer function.

( ) ^{s A} ( ) ^{s G} ( ) ^s

G

_C

=

_OC

⋅

_EA . (4.25) As mentioned in [28], it is desirable to maximize loop gain T in order to achieve the best re-jection of line and load disturbances.

G

_VD(s)

4.2 Controller Design

4.2.1 Model Uncertainty

To investigate the characteristic of the model obtained in preceding section the parallel converter of the design specifications and component values listed in Table 4.1 are taken as an

example. With substituting the parameters in Table 4.1 into equation (4.10), (4.11), and (4.15), it can be seen that the coefficient matrices would vary as the operating point changes, and is so called model uncertainty. The open loop poles and zero of various line phases (

ω

_L

⋅ t

=0 to

π 2

) at a certain condition (Vac=85 Vrms and Pout=30 W) listed in Table 4.2. The effect of the second pole and zero are ignored, because they are both far away from origin and on the left real axis. It can be seen that the dominant pole moves toward origin when phase is near transi-tion angle, which is between

( ^{π 2 0} ) ³

and

( ^{π 2 0} ) ⁴

. In addition, the locations of poles and zeros on both sides of the transition angle violently change when line phase cross the transition an-gle, because the dynamic equations of M1 and M2 modes are quit different. Hence, the closed loop system with designed compensator should be stable over the operation range, especially at the transition angle.

Table 4.1 Converter specifications and parameters of components

v

in 85-265 Vrms

V

_O 54 V

P

_out 60 W

f

S 100 kHz

L

B 35

μ

H

T1

L

M1=145

μ

H; n1=1.6 T2

L

M2=1.4 mH; n2=1.8

S K2968

C

B 470

μ

F/450 V

C

O 1000

μ

F/63 V

Table 4.2 Open loop poles and zero for various phases

NO ωL⋅^t Mode Pole Pole Zero

1 0 M₁ -88.16 -1.6685*10⁵ 2.015*10⁵ 2

(

π 20

)

1 M₁ -86.97 -1.6685*10⁵ 2.425*10⁵ 3

(

π 20

)

2 M1 -83.52 -1.6686*10⁵ 5.9211*10⁵ 4

(

π 20

)

3 M1 -78.14 -1.6688*10⁵-4.7536*10⁵ 5

(

π 20

)

4 M₂ -2.8688 -93.5279 -2.5704 6

(

π 20

)

5 M2 -3.8504 -93.5279 -4.0014 7

(

π 20

)

6 M2 -5.7128 -93.5279 -6.1503 8

(

π 20

)

7 M2 -8.8468 -93.5279 -9.5094 9

(

π ²⁰

)

8 M₂ -13.3798 -93.5279 -14.2412 10

(

π 20

)

9 M2 -18.1843 -93.5279 -19.2016 11 ^{π 2} M2 -20.4032 -93.5279 -21.4826

* Operation conditions is at vac=85 Vrms and Pout=30 W.

4.2.2 Controller design

In order to generate the complex duty dm2 in (4.9), the controlled system had to possess small rising time, low overshoot, and zero steady state error. In addition, the compensator also can generate the correct duty d in (3.3) and (3.6) with different operation modes and points.

Since the coefficient matrices in (4.11) and (4.15) varies as the operating point changes, espe-cially the open loop poles and zero of the system move as the line phase increases and vio-lently change at transition angle. Hence, the compensator is designed so that the loop gain has desired dc gain, gain crossover frequency, and phase margin at the transition angle over the operation range. The feedback control loop shown in Fig. 4.1 is implemented with

Z

C2=RC2+

⋅

1

, ZC3=RC3||

⋅

1

, and ZC4=RC4||

⋅

1

. Consequently, the transfer functions

of error amplifier and compensator can be obtained as In (4.26a), there is a pole at zero frequency so that the gain could be kept high at dc level. The design criteria of the parameters in (4.26c) are shaping the loop frequency response by placing pole

ω

₄ near the crossover frequency

ω

_C, setting the zeros

ω

₂ and

ω

₃ below

ω

_C and near the pole of plant. The good output regulation accuracy can be achieve by increasing dc gain, which can be expressed as

( ) 0

_OC

( ) 0

VC

dc

G A

g = ⋅

(4.27) Consequently, the designed corresponding circuit parameters are listed in Table 4.3. The dc gain

g

_dc, the gain crossover frequencies

ω

_gc, and phase margins Pm of loop gain for various conditions are listed in Table 4.4. It can be seen that the compensated system has dc gain of 58.4818 dB, crossover frequency of 1.3349·10⁵ rad/s and phase margin of 67.5056 degrees at least.

Table 4.3 Parameters of controller and optocoupler circuit

R

O1

22k

Ω

R

E

2.4k

Ω

R

O2

1.05k

Ω

R

F

18k

Ω

R

C2

4.4k

Ω

CTR 1

R

C3

510

Ω

C

C2

22nF

R

C4

33k

Ω

C

C3

100nF

R

sen

0.22

Ω

||1

Ω

C

C4

470pF

Table 4.4 Gain crossover frequency and phase margin for various conditions

Open Loop system Compensated loop NO vac (Vrms) Pout (W) θ_T(rad) Mode

Pole Pole Zero gdc(dB) ω_gc(rad/s) P (deg)_m 1 85 30 0.6271 M1 -71.43 -1.669·10⁵-1.4615·10⁵ 70.3268 1.5334·10⁵ 105.4899 2 85 30 0.6271 M2 -2.8638 -93.5279 -2.5607 74.8905 3.7717·10⁵ 95.1699 3 175 30 0.3721 M1 -91.37 -1.319·10⁵ -3.401·10⁵ 70.2323 1.3430·10⁵ 79.0114 4 175 30 0.3721 M2 -0.5638 -93.5279 -0.09642 58.4818 2.9587·10⁵ 96.5204 5 265 30 0.2743 M1 -105.3 -1.2099·10⁵-6.1354·10⁵ 69.7509 1.3349·10⁵ 67.5056 6 265 30 0.2743 M2 -0.257 -93.5279 0.06242 60.7801 2.7037·10⁵ 97.0965 7 85 60 1.1972 M1 -109.2 -1.7128·10⁵-4.4395·10⁴ 66.4146 5.5232·10⁵ 106.1982 8 85 60 1.1972 M2 -42.5721 -187.0557 -44.9171 76.5502 7.8111·10⁵ 92.5365 9 175 60 0.7706 M1 -113.4 -1.3303·10⁵-6.7166·10⁴ 68.2781 3.6071·10⁵ 105.0967 10 175 60 0.7706 M2 -1.874 -187.0557 -1.9477 74.2250 6.0540·10⁵ 93.2640 11 265 60 0.6609 M1 -121 -1.2156·10⁵-8.0031·10⁴ 68.5006 3.0272·10⁵ 103.4549 12 265 60 0.6609 M2 -0.6273 -187.0557 -0.591 72.5892 5.5262·10⁵ 93.5710

4.3 Simulation and Experimental Results

Since the small-signal behavior predicted by means of the average model cannot be meas-ured with frequency instrument directly, the validation of the proposed model together with designed feedback control loop will be verified in the time domain. The specification of the prototype is shown in Table 4.1, and the parameters of control circuits are shown in Table 4.3.

For comparison purpose, the theoretical model, PSPICE simulation and experimentally measured waveforms of the boost-flyback-flyback at V_ac = 265V_rms and P_out=60W are put

to-gether and shown in Fig. 4.5-4.7 From the waveforms in Fig. 4.5 and 4.6, it is clear that the theoretical model and PSPICE simulation waveforms correspond very well in <i_LB>, <i_DB>,

<iDI1>, <iDO1>, and <iDO2>. The waveforms correspond well in d for M2 mode, but PSPICE d waveform for M₁ mode varies because of the feedback effect of v_O ripple. Furthermore, the PSPICE simulation and experimentally measured waveforms are similar in iac shape and steadily stable in v_O in Fig. 4.6 and 4.7. It can be seen in Fig. 4.7 that i_ac is slightly distorted form <iLB> because of the characteristics of line filter and snubber. This doesn’t affect dis-cerning the modes of M₁ and M₂. Hence the theoretical model can be verified.

To show the input current shape and output voltage regulation, the measured power factor, output voltage, and output ripple with different line inputs and output loads are given in Table 4.5. The maximum output ripple is 170.573 mV, and occurs at 265 Vrms and 60 W. The data tabulation shows that the converter with properly designed controller has high power factor and small steady state error over the entire operation range.

The PSPICE dynamic waveforms for positive load changing from 97.2 Ω to 48.6 Ω are shown in Fig. 4.8(a), and waveforms for negative load changing from 48.6 Ω to 97.2 Ω are shown in Fig. 4.8(b), both Fig 4.8(a) and (b) are at V_ac = 85 V_rms. The output ripple voltages are 0.21 V at 97.2 Ω and 0.26 V at 48.6 Ω, the steady state error is smaller than 0.5%, and the settling time is small than 1.111 ms. The measured dynamic waveforms for positive load stepping from 0.555 A to 1.110 A are shown in Fig. 4.9(a), and waveforms for negative load changing from 1.110 A to 0.555 A are shown in Fig. 4.9(b), both Fig 4.9(a) and (b) are at V_ac

= 85 Vrms. The overshoot or dropped voltages are small than 0.1 V, the settling time is small than 2 ms, and the output ripple voltage is very small. Accordingly, the simulation and ex-periment results in Fig. 4.8 and Fig. 4.9 match well in the superior dynamic response. More-over, the duty cycle and the line current are adjusted to the new load conditions instantane-ously. Hence, the converter does not require several line cycles to reach the new steady state conditions. Because the controlled system possesses fast dynamic response and tightly

regu-lated output voltage, the <iac> can have low harmonics and high power factor as shown in Ta-ble 4.5.

0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.055 0.06 0.065

0 0.2 0.4

0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.055 0.06 0.065

0 0.2 0.4

0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.055 0.06 0.065

0 0.2 0.4

0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.055 0.06 0.065

0 0.5 1

<i

_LB

>

<i

_DB

> <i

_DI1

>

<i

_DO2

>

<i

_DO1

>

d

Fig. 4.5 Theoretical waveforms of the parallel boost-flyback-flyback converter at Vac = 265 Vrms and Pout=60 W.

i

_ac

<i

_LB

>

<i

_DB

> <i

_DI1

>

d

<i

_DO1

>

<i

_DO2

>

v

_O

0 0.2 0.4

Fig. 4.6 PSPICE simulation waveforms of the parallel boost-flyback-flyback converter at V_ac = 265 V_rms and P_out=60 W.

v_ac: 200 V/div, i_ac: 0.2 A/div, v_O: 1.0 V/div

i

_ac

v

_ac

v

_O

v

_{O, p-p}

v

_{O, ave}

5 ms 0.2 A

1.0 V 200 V

Fig. 4.7 Experimental waveforms of the parallel boost-flyback-flyback converter at V_ac = 265 V_rms and P_out=60 W.

Fig. 4.7 Experimental waveforms of the parallel boost-flyback-flyback converter at V_ac = 265 V_rms and P_out=60 W.

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