In this chapter, a novel surface micromachining-like fabrication process is used to integrate SOI and SU-8 in an optical bench, including grating plate, beam splitter, reflective mirror, Fresnel lens, and photo-detector. Using SOI wafer can simplify the process flow. The optical components are made not only in silicon nitride but also by SU-8. The optical bench assembled by bimorph stress beams is discussed in first part.
The second part discusses the process for surface tension by melting solder ball.
Finally, some phenomena and problems will be discussed.
3–1 Optical bench – integration of SOI and SU-8
Flatness is an important issue for optical components. Since the SCS layer almost has no stress, it can provide a flat surface for the optical purpose. Therefore, the basic structures of the bench are defined on the device layer of SOI substrate. The silicon nitride layer is an isolation layer for conducting wires and separates the p+ and n+ regions of photo diode. In addition, it is commonly used as an optical material.
Silicon oxide is a sacrificial layer. Gold is the material for conductive wires and reflective mirror. Finally, SU-8 is used for the bimorph stress beam and anchor structure. Furthermore, it also can be used as the optical elements. Figure 3-1 is a schematic of the cross-section of a completed device, including the photo detector, 135∘reflective mirror and an optical element.
SU-8/SCS stress beam
Optical element
(Silicon nitride or SU-8)
Most fabrication processes were executed in the Nano Facility Center at National Chiao Tung University. The process flow is showed in Figure 3-2. The detailed parameters of the process will be described later.
Process Flow
Step (A): The device layer (resistivity: 1-10 ohm-cm, thickness: 5 μm) of SOI wafer was pattern by photolithograph. The main device structure was defined by
inductively coupled plasma reactive ion etching (ICP DRIE). (Mask #1) Step (B): low stress Si3N4 was deposited by Low Pressure Chemical Vapor Deposition
(LPCVD) and patterned by reactive ion etching (RIE). (Mask #2) Step (C): Boron (B) was implanted for the P+ region of the photo detector.
Step (D): Si3N4 was patterned by RIE again. Then arsenic (As) was implanted for the N+ region of the photo detector. (Mask #3)
Figure 3–1: Schematic of structures and materials Anchor cap and
rotational hinge Incident
light
SOI substrate
Figure 3–2: Fabrication process of the optical bench with stress beam.
SiO2 Si3N4 PR
SOI Substrate
Step (E): SiO2 was deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD). Aluminum was deposited on SiO2 by thermal coater. They were patterned by High Density Plasma RIE (HDP-RIE) respectively. (Mask #4) Step (F): Aluminum and SiO2 were pattern by HDP-RIE again. (Mask #5)
Step (G): Photoresist AZ4620 was coated and patterned for the following lift-off step.
(Mask #6) Step (H): Gold was sputtered by DC Sputter system.
Step ( I ): Photoresist was removed by acetone. Au is patterned by lift-off.
Step ( J ): SU-8 was coated and patterned. (Mask #7) Step (K): SiO2 was etched by HF. The structures were released by HF vapor.
(A) Device layer of the SOI wafer patterned by photolithograph; main device structure defined by ICP DRIE (Mask # 1)
(B) Low stress Si3N4 deposited by LPCVD and pattern Si3N4 by RIE (Mask # 2)
SiO2
SOI Substrate
SOI Substrate Si3N4 P+ region
SOI Substrate SOI Substrate
SiO2 Si3N4 P+ region N+ region Al
SOI Substrate
SiO2 Si3N4 P+ region N+ region
Figure 3–2: Fabrication process of the optical bench with stress beam (continued).
(C) P+ region of the photo detector ion implanted (B); photoresist removed SiO2
(D) Si3N4 patterned by Poly-RIE; N+ region ion implanted (As); photoresist removed (Mask # 3)
SiO2 Si3N4 P+ region N+ region
(E) SiO2 deposited by PECVD and aluminum deposited by thermal coater; aluminum and SiO2 patterned by HDP-RIE; photoresist removed (Mask # 4)
(F) Aluminum and SiO2 patterned by HDP-RIE; aluminum and photoresist removed (Mask # 5)
SOI Substrate
SiO2 Si3N4 P+ region N+ region PR
SOI Substrate
SiO2 Si3N4 P+ region N+ region PR Au
SOI Substrate
SiO2 Si3N4 P+ region N+ region Au
SOI Substrate
SiO2 Si3N4 P+ region N+ region Au
Figure 3–2: Fabrication process of the optical bench with stress beam (continued).
(G) Photoresist AZ4620 coated and patterned (Mask # 6)
(H) Gold sputtered by DC Sputter system
(I) Photoresist removed; gold patterned by lift-off
(J) SU-8 coated and patterned (Mask # 7) SU-8
SOI Substrate
SiO2 Si3N4 P+ region N+ region Au
Figure 3–2: Fabrication process of the optical bench with stress beam (continued).
3–1–1 Fabrication technology
In this section, the detailed fabrication parameters of the above process are described. A standard RCA clean process was first performed on the bare SOI wafer.
In the first step, the photoresist FH6400 was spin coated on the bare SOI wafer with the recipe of spread cycle speed = 1000 rpm for 10 seconds and spin cycle speed = 4000 rpm for 30 seconds. After exposure and development of the photoresist, ICP DRIE was used to anisotropicaly etch the 5 μm-thick single crystal silicon of the SOI device layer. The photoresist was used as the etching mask. The main structures, including the frame of the optical components and reflective mirror surfaces, were defined in this step. The photoresist can then be removed by acetone in a shaker or immersing in H2SO4. Before depositing low stress silicon nitride, the SOI wafer was dipped in HF solution. The native oxide on the device layer can be removed by HF.
Then a 0.6-μm-thick low stress Si3N4 was deposited by LPCVD with the recipe of NH3 flow rate = 17 sccm, SiHCl2 flow rate = 85 sccm, temperature = 850℃ and pressure = 180 mTorr. It took 75 minutes to deposit this thin film. After deposition, HMDS was coated on the surface of the Si3N4 layer. HMDS can strengthen the adhesion between photoresist and Si3N4, SiO2, or metal. Next the AZ4620 photoresist was spin coated with the recipe of spread cycle speed = 1000 rpm for 10 seconds and (K) Sacrificial layer SiO2 etched; structures released by HF vapor
SU-8
spin cycle speed = 3500 rpm for 30 seconds, followed by exposure and development.
It was used not only as a mask for the P+ ion implantation but also for the optical elements, such as grating, polarize beam splitter and Fresnel lens. RIE of Si3N4
defined the P+ implantation region and the optical elements.
The implantation process was performed at National Nano Device Laboratories.
Boron was used to form the P+ region in the n-type device layer. The implantation energy was 15 keV and the concentration of dopant is 5×1014 cm-2. Photoresist was removed subsequently. The sample was then annealed at 900°C for 10 sec to activate the dopants. The N+ region was also defined by the photolithography of AZ4620 and RIE of SI3N4. Arsenic was the dopant for the N+ region. The implantation energy was 60 keV, and the concentration of dopant was 5×1015 cm2. The photoresist was then removed. Then the sample was annealed at 900˚C for 15 sec to activate the dopants.
Sometimes, it was not easy to remove the photoresist by ACE or H2SO4 because it was burned during the implantation process. In such cases, O2 plasma can be used to remove the burned photoresist.
In the next step, 3-μm-thick SiO2 was deposited by PECVD on the top side of the SOI wafer. This is a sacrificial layer for the free rotation space in the anchor.
Aluminum was coated on this SiO2 layer as the etching hard mask. The deposition time of the 3-μm SiO2 layer with 400 sccm O2 and 10 sccm tetraethoxysilane (TEOS) at 300℃, 300 mTorr chamber pressure and 200 W RF power was about 13 minutes.
5000-Å-thick Al was then deposited by thermal evaporation. Before deposition, clean and dipping in Buffered Oxide Etchant (BOE) was necessary. After coating and patterning with AZ4620, aluminum was etched by HDP-RIE with the recipe of 35 sccm BCl3, 35 sccm Cl2, 10 mTorr chamber pressure, 750 W ICP RF power and the etching time is 50 seconds. Subsequently, photoresist was removed and the 5 μm-thick SiO2, 3 μm PECVD oxide layer and 2 μm-thick thermal oxide of SOI, were also
etched by HDPRIE. The etching time of 5 μm oxide with the recipe of 40 sccm CHF3, 40 sccm Ar, 10 mTorr chamber pressure and 750 W ICP RF power is about 30 minutes. The position of anchor cap is defined in this step.
In the following step, the aluminum remained from the last step was patterned again with AZ4620 as the hard mask. The 3-μm-thick PECVD SiO2 was then etched with the same recipe as the last etching and the etching time was about 18 minutes.
Windows of contact of the SOI device layer with gold and with SU-8 were opened in this step.
After coating and patterning of AZ4620 again, chromium (300Å) and gold (1000Å) were deposited by DC sputtering. Chromium was an adhesion layer between silicon and gold. Then, the photoresist and unwanted metal atop the photoresist were removed in an acetone bath. Note that it was necessary to dip the wafer in diluted HF solution before depositing the gold and its adhesion layer, chromium. Otherwise, the gold layer may be deposited on the native oxide and may peel off after releasing devices.
SU-8 was spin-coated and patterned used in the next step with the recipe of spread cycle speed = 500 rpm for 5 seconds, spin cycle speed 3000 rpm for 30 seconds, pre-bake at 65°C for 1 minute and soft bake at 95°C for 2 minutes. The exposure time was 4 seconds, and post exposure bake at 65°C for 1 minute and 95°C for 2 minutes. The development time in SU-8 developer was 3 minutes and hard bake time was 20 minutes at 200°C. In the next step, devices were released when the sacrificial oxide layer was removed by the vapor of 49% HF solution and rinsed in IPA. The final assembly was done by probe with manual operation.
SOI Substrate
Figure 3–3: Fabrication process of the optical bench with surface tension.
SiO2
3–2 Fabrication process of self-assembly by surface tension
The failure of manual assembly in the above process is a big problem. To avoid manual operation, the surface tension self-assembly is introduced in the fabrication process. It also simplifies the process because the sacrificial layer can be canceled, as discussed in the following.
Figure 3-3 shows the diagram of the fabrication process. Step (A) to (D) were the same as for the process with stress beam. The sacrificial oxide layer deposition was eliminated. Gold was deposited and patterned by lift-off in steps (E), (F) and (G). The gold layer was used not only as the conductive wire and reflective surface but also the adhesion layer between silicon and solder.
In the next step (H), solder ball should be pressed first. The flat solder was then put on the adhesion pad of gold and pre-melted.
In the final step (I), the sacrificial layer SiO2 was removed first by HF vapor.
Solder was then melted again. Structures were assembled by the surface tension when solder was melted.
(A) Device layer of the SOI etched by ICP DRIE (Mask #1)
SOI Substrate
SiO2 Si3N4 P+ region N+ region PR Au
SOI Substrate
SiO2 Si3N4 P+ region N+ region Au
Figure 3–3: Fabrication process of the optical bench with surface tension (continued).
(E) and (F) Photoresist AZ4620 coated and patterned; gold sputtered by DC Sputter system (Mask # 4)
(G) Photoresis removed; gold patterned by lift-off.
SiO2 Si3N4 PR
(B) Low stress Si3N4 deposited by LPCVD; Si3N4patterned by RIE (Mask #2) .
SOI Substrate
SiO2 Si3N4 P+ region N+ region
(C) and (D) P+ region ion implanted (B); remove photoresit; Si3N4 patterned by RIE; N+ region ion implanted (As); remove photoresit. (Mask #3)
SOI Substrate
SOI Substrate
SiO2 Si3N4 P+ region N+ region Au SOI Substrate
SiO2 Si3N4 P+ region N+ region Au Limiter structure
Figure 3–3: Fabrication process of the optical bench with surface tension (continued).
Solder (H) Solder ball placed on pad and pre-melted.
Solder
(I) Sacrificial layer SiO2 etched; release structure by HF vapor; solder melted again;
structure assembled by surface tension.
The two processes are compared in Table 3-1. The solder reflow uses only five masks. This really eliminates some complicated steps.
Purpose of stress beam assembly Purpose of self-assembly Mask 1 Device layer of the SOI wafer; frame
of optical elements, reflective mirror surfaces, and stress beams
Device layer of the SOI wafer; frame of optical elements, reflective mirror surfaces, and stress beams
Mask 2 Si3N4; optical elements, isolation layer, and P+ region
Si3N4; optical elements, isolation layer, and P+ region
Mask 3 Si3N4;N+ region Si3N4;N+ region Mask 4 Aluminum and SiO2; position of
anchors
Mask 5 Aluminum and SiO2; contact region of the SOI device layer with gold and with SU-8
Mask 6 Gold; lift-off Gold; lift-off Mask 7 SU-8; anchor, stress beam, and
optical elements
SU-8; optical elements
Release Release and assembly by manual Pre-melt, release, and reflow again for assembly
Table 3-1: Comparison of the two fabrication processes.
3–3 Problems and discussions about fabrication process
Some problems and phenomena occurred in the fabrication processes. They are discussed in this section.
(1) Photolithography of Si3N4 optical element
In the second mask step, thin Si3N4 film was pattern for the Fresnel lens. The Fresnel was composed of concentric rings. The innermost ring had the largest width and the width of rings decreased progressively. It means that the width of the outermost ring can be very small. Further, there were many release holes on the frame and reflective mirrors. The depth of these release holes was 5 μm. After the release hole was opened, Si3N4 was deposited by LPCVD with good step coverage, as shown in Figure 3-4. When photoresist was next spin coated on the wafer, the release hole was filled with photoresist. If a 2-μm-thick photoresist AZ4620 was spin coated on the top surface, the exposure time for the 2-μm-thick photoresist was not enough to exposure the photoresist in holes. The window of release holes was not opened after Si3N4 RIE because there was photoresist remaining in the hole, as shown in Figure 3-4 (a). This is a problem at the releasing step. Extending the exposure time is a direct solution to remove the residual photoresist in the hole. The outer rings of the Fresnel lens were etched, as shown in Figure 3-5. The line width was decreased by the over exposure, so the outer rings disappeared. Another problem in this step was that the area of release hole was reduced due to the Si3N4 on the side wall, as shown in Figure 3-4 (b). Negative photoresist can be used in this photolithography to solve this problem.
Released hole and SI3N4 deposit
Release hole is filled with photoresist
Exposure for 2μm
Over exposure
RIE of 0.6μm Si3N4; remove photoresist
RIE of 0.6μm Si3N4
Figure 3-4: Problems in Si3N4 etching: (a) covered release hole (b) narrowed release hole
Silicon SiO2
Si3N4 PR
Figure 3-5: Disappearance of the outer rings (a)
(b)
(2) Aluminum hard mask
In the step of Mask 4, photorsist was first used as the RIE mask. The etching time of the 5-μm-thick SiO2 were long and the photoresist mask would also be etched.
So, the photoresist must be very thick. The thick-film photoresist AZ4620 would collapse during hard bake, as showing in Figure 3-6. This would cause the non-vertical shape and reduce sacrificial oxidation thickness. The free rotational spaces for the hinge were therefore reduced, as shown in Figure 3-7. If aluminum is used as the hard mask, the vertical shape will be retained, as shown in Figure 3-8.
Shape of photoresist before hard
Figure 3-6: The shapes of PR before and after hard bake
Shape of photoresist after hard bake
Figure 3-7: Non-vertical and reduced hinge rotational space.
(3) Over etching silicon oxide in the step of Mask 5
In the Mask 5 step, silicon oxide is etched to open the silicon region for gold and SU-8 contact. So, it is very important to remove the silicon oxide completely to prevent the SU-8 and gold layer from peeling off at the releasing step. But the RIE etches not only silicon oxide but also silicon. If silicon surface is etched, the shallow ion implantation for contacts and photodiodes will be affected. This problem can be avoided by a two-step etching process. The RIE process first etches silicon oxide for almost 3 μm, and then the wafer is dipped in diluted HF solution to etch the remaining oxide.
However, the etching time is hard to control. Therefore, the solder reflow self-assembly is investigated to avoid the use of the sacrificial oxide layer, as will be discussed in the next section.
(4) Solder ball self-assembly process
To use the solder ball for self-assembly, solder balls were pressed first and then Figure 3-8: Vertical shape for 5μm-thick SiO2 etching.
5μm SiO2
5000 Å Al
put on the pad with the flux to improve the adhesion between the solder and the gold.
Flux can etch the oxide on the solder to enhance the electrical conductivity. Solder covered and stuck to the pad after pre-melt at 240°C with flux, as shown in Figure 3-9.
The flux was removed by water after pre-melt, as shown in Figure 3-9 (b). But some of the flux mixed in the solder may be an impurity for this assembly.
Although the adhesion problem can be solved by flux, the released devices still did not lift-up during the final melt, as shown in Figure 3-10. They may have two reasons. First is the stiction of the large plate structure. Second is the shape of melted solder ball. Stiction can be improved by CO2 dryer or back-side etching. But the non uniform solder shape after melting is the most important problem, as shown in Figure 3-11.
Figure 3-9: Solder ball place on gold pad (a) pre-melt with flux, (b) clean by water
(a) (b)
Figure 3-10: Assembly is failure after solder melt
(c) (d) Figure 3-11: (a) and (b) are the different shapes discovered on the same chip. (c)
and (d) are the cross section view of (a) and (b).
(a) (b)
The melted solder should be able to cover the full pad and has an arc shape, as shown in Figure 3-12 (a). In the experiment, the pad was not entirely covered by the solder, as shown in Figure 3-12(b).
The power of rotation is the surface energy of solder in this assembly approach.
The surface energy of solder should be translated into the work to rotate the plate. The device was not released during the pre-melt, so surface energy of the solder might be reduced to a balanced state. After the devices were released and solders were melted again, the shape of solder did not change too much. This should be an important issue in this method. Some solutions of the above problems will be proposed and discussed in Chapter 5.
Solder Gold pad layer Silicon substrate
Full cover (a) Solder covers the entire pad region.
(b) Solders do not cover the entire pad and have different melted shapes.
Non-entirely cover Different shape
after melt
Figure 3-12: Schematic and SEM for solder melt
(5) Latch structure design
One of the latch designs was not appropriate for assembly using probe. The layout is shown in Figure 3-13. Probe was hard to pick it up because the width was just 12 μm. The neck was easily broken when being picked up from side.
3–4 Summary
Two fabrication processes were investigated in this chapter. Although there were some problems in the original integrated SOI and SU-8 process, they were solved by changing the materials or adjusting process parameters. In order to improve the yield of assembly, the manual assembly can be replaced by self assembly. This was the first attempt to use the solder reflow for self-assembly. Although the result was not successful, some important issues were discovered in this experiment.
12 μm neck
Figure 3-13: Layout of the inappropriate latch structure
Chapter 4
Experiment Results and Measurement
This chapter presents the results of experiment and the measurement. The first part shows the measurement of SU-8/Single Crystal Silicon stress beam. The integrated devices are shown in the second part. The scanning electron microscopy (SEM) photographs and the optical measurement of individual devices are shown.
Finally, the photo diode is discussed.
4–1 SU8/Single Crystal Silicon Stress Beam
In the releasing process, the frame of lens or mirror is lifted up by the stress
In the releasing process, the frame of lens or mirror is lifted up by the stress