Detailed fabrication process flows and process issues encountered in the SOI based devices are presented in this chapter. The first section of this chapter shows the processes based on SOI wafers. The processes include wafer cleaning, photolithography, deep reactive ion etching, structure releasing, and metal deposition.
The second part discusses the process issues which were encountered in the experiments. The problems were solved and devices were successfully fabricated.
3.1 Fabrication process flow
As mentioned in Chapter 2, the high aspect ratio MEMS comb finger structures serve the variable capacitor to convert energy. The structure is fabricated by the deep reactive ion etching technology. Inductively Couple Plasma (ICP) etching is used in our case. The comb fingers attached to the moving plate are the moving electrodes of the variable capacitor. The fingers on outer frame serve as the fixed electrodes of the variable capacitor.
To obtain the maximum output power, the device thickness should be as large as possible. However, it is limited by the ICP fabrication capability to define the finger structure. The resistive loss was reduced by using a highly conductive device layer with a resistivity less than 0.02 Ω-cm. The buried oxide layer is 2 μm. The handle layer is 400 μm for a firm structural support.
Most of the fabrication was conducted in the Nano Facility Center at National Chiao Tung University. The fabrication process is illustrated in Fig. 3.1 and the detail of the parameters in every process step is presented in the following sections.
Step 1: Wafer cleaning
RCA cleaning is an industrial standard process for removing contaminants from wafers. It should be performed before high temperature processing steps to minimize defects in following processes. The procedure has three major steps in sequence:
A. Organic Clean: Removal of insoluble organic contaminants B. Oxide Strip: Removal of the thin silicon dioxide layer.
C. Ionic Clean: Removal of ionic and heavy metal atomic contaminants.
The SOI wafer is first cleaned with the following parameters and steps, as shown in Fig. 3.1(a). Every step begins and ends with 5 minute de-ionized water (DI water) rinse.
Step Process parameters Function
1 H2SO4 : H2O2 = 3 : 1 (10 min 85 °C) Organic removal 2 HF : H2O = 1 :100 (room temperature 30 seconds) Chemical oxide removal 3 NH4OH : H2O2 : H2O = 1 : 4 : 20 (10 min 85 °C) Particle removal 4 HCl : H2O2 : H2O = 1 : 1 : 6 (10 min 85 °C) Ion removal 5 HF : H2O = 1 :100 (room temperature 30 seconds) Chemical oxide removal
Step 2: Silicon oxide deposition on the backside
Silicon oxide was deposited by a BR-2000LL plasma enhanced chemical vapor deposition (PECVD) system on the back side of the SOI handle wafer, as shown in Fig. 3.1(b). The silicon oxide serves as the hard mask for the following backside ICP etching process due to the relatively superior heat dissipation in the ICP etching process.
A 4.5-μm-thick silicon oxide is required according to the selectivity of 100:1 between silicon and silicon oxide in the ICP process. Deposition was divided into several 2.2 μm steps to prevent cracking of oxide layer due to residual stress. Detailed
parameters are given as below.
Description Process parameters
SiH4 flow rate 5 sccm
N2O flow rate 90 sccm
Process pressure 400 mTorr
Process temperature 350 °C
RF power 11 W
Deposition rate 35 minutes resulting in 2.2 μm (repeat 2 times)
Step 3: Backside photolithography on silicon oxide
The backside photolithography was performed on an EV620 aligner on the silicon oxide deposited in the previous step, as shown in Fig. 3.1 (c). The photoresist was AZ4620 due to its available thickness in the spin coater. The thickness of AZ4620 was 7 μm according to the selectivity between AZ4620 and oxide in the buried oxide etchant (BOE). The photoresist mask should be hard baked for at least 1 hour before wet etching to ensure the material integrity. Detail parameters are given as below.
Step Description Process parameters
1 HMDS coating 150 °C 30 minutes
7 Development 80 seconds
8 DI water Rinsing 90 seconds
9 Hard bake 120 °C at least 1 hour
Step 4: Backside wet etching of silicon dioxide
This step is shown in Fig. 3.1(d). The silicon oxide below the photoresist was etched by a buffered oxide etchant (NH4F: HF=6:1) with an etch rate of 1 μm per minute roughly. Due to the relatively low selectivity between silicon oxide and photoresist in the RIE process, we used BOE solution instead. The undercutting effect of wet etching was minimal and did not cause the pattern to peel off from the substrate. The samples than were immersed in DI water to wash off the BOE solvent to protect the photoresist mask from further BOE attack and prevent the peeling off problem.
Step 5: Frontside photolithography
The frontside photolithography was performed on an EV620 double side aligner to define the photoresist mask, as shown in Fig. 3.1(e). The subsequent ICP etching is the primary process to define the device structure. In order to protect the structure in the device layer, the frontside photolithography is performed after the backside etching process. The photoresist thickness is 5 μm because the minimum selectivity of ICP etching between silicon and AZ4620 photoresist is 40:1. Hard bake should be as long as possible to withstand the ICP etching. Detailed parameters are given below:
Step Description Process parameters
1 HMDS coating 150 °C 30 minutes
7 Development 60 seconds
8 DI water Rinsing 90 seconds
Step 6: Frontside deep reactive ion etching
The silicon structure in the device layer is defined by ICP etching which is performed by using a STS MESC multiplex ICP reactor with standard Bosch processes, as shown in Fig. 3.1(f). By applying suitable etching and passivation parameters, a better etching profile can be ensured. The details will be discussed later.
In order to maintain a uniform etch rate and better heat dissipation, maximum helium leak rate should be limited. The averaged etch rate is roughly 2 μm per minute.
Detailed parameters are given as below.
Description Etch phase parameters Passivation phase parameters
Time per cycle 11.5 seconds 7.0 seconds
SF6 flow rate 130 sccm 0 sccm
Helium back side pressure = 10 Torr Maximum helium leak up rate = 20 mTorr/min Etch rate 0.6-0.7 μm per cycle depending on pattern
Step 7: Wafer dicing
Wafer dicing must be performed before the backside deep silicon etching. The reason is that the entire wafer becomes very fragile and may disintegrate in the reactor chamber when a large area of the backside silicon is removed. The other problem is that the residual stress in the buried oxide can damage the structures in the frontside layer. Therefore, the wafer is diced first by a Disco 2H/6T system. The structures in the device layer are protected during the dicing process by a 7-μm-thick AZ4620
photoresist. The detailed parameters of the protection photoresist coating are given as below. The subsequent backside etching will be conducted with the individual chips bonded to a carrier wafer with thermal grease.
Step Description Process parameters
1 Photoresist mask removal A.C.E or H2SO4 2 1st spin (spread cycle) 500 rpm 10 seconds 3 2nd spin (spin cycle) 1800 rpm 40 seconds
4 Soft bake 20 minutes
Step 8: Backside deep reactive ion etching
Diced chips were bonded on a carrier wafer with thermal grease. The thickness of thermal grease should be limited and it should be applied to the peripheral areas to prevent contamination of the chips. In order to prevent the rupture of the carrier wafer, silicon oxide should be deposited on the carrier wafer before the chip bonding to avoid the plasma attacking during the ICP process. The process of the backside ICP etching is shown in Fig. 3.1 (g). Heat dissipation issues due to poor helium cooling capability on the bonded chip could jeopardize the selectivity and vertical profiles of the etched sidewalls. Fortunately, the backside structure is rather insensitive to or even benefiting from the non-vertical etching profiles. Since the goal of this step is creating holes to allow HF to attack buried oxide in the release step, a larger contact area caused by non-vertical profiles is beneficial in the following process. The process parameters are identical to these for the frontside ICP process in step 6.
Step 9: HF Release
The chip is released by 49 % HF to remove the unwanted buried oxide and the blocking structure in the handle layer. The process is shown in Fig. 3.1 (h). HF vapor
The release time using 49% HF is about 20 min and the oxide layer is over etched in order to prevent shortage during metal deposition. Finally, the device is cleaned by rinsing in isopropanol (IPA) and then hot baked after the release is finished.
DI water cannot be used for cleaning to avoid the stiction between the comb fingers in the release process.
Step 10: Silicon nitride deposition
In our design, a dielectric layer is applied on the fingers to avoid contact shortage. Silicon nitride is chosen because it is a good dielectric material with high dielectric constant (εr = ). Low-pressure chemical vapor deposition (LPCVD) is 7 used to deposit a 500-Å-thick sidewall nitride.
The original process using plasma-enhanced chemical vapor deposition (PECVD) was proved to be less efficient due to poor lateral coverage. Due to the poor selectivity between the silicon nitride and silicon oxide, HF release is performed before silicon nitrite deposition.
Step 11: Silicon nitride removal in anchor areas
After the silicon nitride was deposited, the top side silicon nitride layer on the anchor area should be removed by a SAMCO RIE-10N RIE in order to provide the electrical contact to the silicon device, as shown in Fig. 3.1 (j). To prevent the shortage between the fingers, the silicon nitride deposited on the top side of the comb finger cannot be removed.
With Shadow mask A in Fig. 3.1 (j), the silicon nitride is protected in the RIE process. Detailed parameters are given as below.
Description Process parameters
SF6 flow rate 30 sccm
CHF3 flow rate 10 sccm
Helium backside cooling 15 sccm
Process pressure 50 mTorr
RF power 100 W
Etch rate 1000 Å per minute
Step 12: Metal deposition
As shown in Fig. 3.1(k), gold is deposited on the contact pads and the lateral contacts in the mechanical switches. With Shadow mask B in Fig. 3.1 (k), gold is only applied to the contact pad and the switch gap areas to prevent unwanted electrical conduction. E-gun evaporator was used in this process and the step coverage is better than our expectation. Titanium or Chromium must be applied as the adhesion layer to prevent gold from peeling off. Gold is used on contact switches and electrodes because of its good resistance to oxidative corrosion and excellent quality as a conductor of electricity. Aluminum should not be used because of its poor oxidation resistance. The detail process parameters are shown below:
Description Process parameters
Ti/Cr deposition 1000 Å
Au deposition 4000 Å
Step 13: Wire bonding and external mass attachment
The last two steps are to bond wires from the contact pads to a PCB and then attach the external mass to the center hole to complete the device, as shown in Fig. 3.1 (l). The chip is attached to the PCB board with silver glue before wire bonding. Other adhesive material can also be used. The ball has a mass of 4 grams and is attached by epoxy. Care must be taken in this step otherwise the device may be broken.
(a) RCA cleaning (Step 1)
(b) PECVD silicon oxide deposition on the backside (Step 2)
(c) Silicon oxide patterning by photoresist (Step 3)
Photo resist Oxide
Silicon Nitride Gold
(d) Silicon oxide hard mask etching by BOE (Step 4)
Fig. 3.1 Fabrication process flow of the SOI device
(e) Front side photoresist patterned by double side photolithography (Step 5)
(f) ICP deep silicon etching on the front side (Step 6)
(g) Back side ICP deep silicon etching (Step 8)
Photo resist Oxide
Silicon Nitride Gold
(h) Release in HF solution (Step 9)
(i) Silicon nitride deposition by LPCVD (Step 10)
Shadow mask A
(j) Top side silicon nitride removal by RIE with Shadow mask A (Step 11)
(k) Metal deposition by sputtering with Shadow mask B (Step 12) Shadow mask B
Photo resist Oxide
Silicon Nitride Gold
Fig. 3.1 Fabrication process flow of the SOI device (continued)
Fig. 3.1 Fabrication process flow on the SOI device (continued)
3.2 Processing issues and solution
A number of problems occurred in our fabrication. One of the problems is caused by the ICP etching process. Another major problem is the shortage of fingers due to poor isolation. This is the cause of parasitic conduction. Several procedures were taken in order to overcome those difficulties.
3.2.1 Non-ideal effects in the ICP process
Inevitably, non-ideal effects exist due to process inaccuracy. The effects include notching, loading effect, sidewall flatness, etc. The detail process will be discussed in the following sections.
Notching effect
Deep reactive ion etching through the silicon device layer is an essential step in microstructure fabrication. However, plasma etching the silicon over an insulator layer has a silicon notching problem at the silicon/insulator interface. The
Tungsten ball Switch Fingers
(l) Wire bonding and tungsten ball attachment (Step 13)
isolation layer causes deflection of reactant ion and forwarding scattering. The poor profile caused by the notching may result in degraded performances. As this undercutting is aspect ratio dependent, the profiles and the characteristics of the final devices may further vary across the wafer, affecting the repeatability and reliability, especially for thick device layers.
Fig. 3.2 Notching effect (a) schematic and (b) SEM micrograph [42]
The problem was encountered in our device structure, as shown in Fig. 3.3 (a).
The bottom of the comb fingers was over etched due to the plasma bombarding on the interface between silicon and oxide. Therefore, the deep ion etching was divided into several steps to prevent over etching. The etch rate of the deep silicon etching should be controlled accurately. Once the depth of etching is approaching the estimated value, devices should be examined by an optical microscope to ensure the overetching is minimized. A better profile of comb fingers is shown in Fig. 3.3 (b) [2]
Fig. 3.3 (a) Notching occurred on the finger’s bottom, (b) improved result [2]
Loading effect
The loading effect is an important issue for the ICP etching process. This effect indicates that the etch rate will be severely reduced when the number of chips and percentage of the etched silicon area is too large [44]. It also happens in our device during the backside ICP etching. The etch rate in the ICP process is 0.6 μm per cycle with six chips but is reduced to about 0.56 μm with ten chips bonded on the carrier wafer. The etched silicon area is proportional to the number of chips bonded on the wafer. More chips on the carrier wafer also cause poor heat dissipation and reduce the etch rate of silicon.
3.2.2 Silicon nitride deposition
Silicon nitride is the material for the isolation layer. Many issues should be considered in the deposition process.
Shortage problem
Previously in our study, silicon nitride was deposited by plasma enhance chemical vapor deposition (PECVD) after the HF releasing. Nitride coated by
(a) (b) Over etched silicon
PECVD has low thermal stress compare with LPCVD. However, the technology suffers from poor step coverage on the sidewalls and the bottom corners, as shown in Fig. 3.4. This result causes shortage if the variable capacitor fingers touch one another.
In addition, particles were produced to influence the deposition quality in the PECVD process [45]. Therefore, LPCVD nitride is adopted due to its better step coverage.
Fig. 3.4 Schematic of poor step coverage
Residue stress in LPCVD silicon nitride layer
Residue stress during the deposition is an important issue. The thickness of LPCVD silicon nitride should be considered or else the residue stress may leads to structure deformation or lifetime reduction. Fortunately, the effect of the residual stress in silicon nitride is ignorable in our case because the wafer is diced before nitride deposition. The properties of the LPCVD and PECVD nitride are listed in Table 3.1 [46]. We deposit a 3000Å-thick LPCVD silicon nitride and expect a 500Å-thick lateral silicon nitride coating based on empirical data.
Silicon Oxide Nitride
Conduction Movable
electrode
Fixed electrode
Table 3.1 Thin film property of LPCVD and PECVD nitride [46]
Deposition type LPCVD PECVD
Typical temperature(oC) 750~850 250~350
Density (g/cm3) 2.9 to 3.1 2.4 to 2.8
Resistivity(Ω.cm) 1016 106 to 1015
Dielectric strength (106 V/cm) 10 5
Stress (M Pa) 1000 (tens.) 200(comp.) to 500 (tens.)
3.2.3 Metal deposition issues
Shadow mask
Shadow masks produced with highly accuracy must be applied in order to prevent metal conduction at the bottom gap between anchors. The shadow mask was made of silicon and the open windows were defined by normal photolithography and ICP etching. The Shadow mask is a 14mm × 14mm square as shown in Fig. 3.5. The experiment result is shown in Fig 3.6. The metal regions are successfully separated.
Fig. 3.5 Shadow mask
(a) (b)
Fig. 3.6 (a) Gold deposition on SW1 and anchors (b) Gold deposition on SW2
Sidewall metal contact
Contact switches are critical for the device to work properly. Previously in our study [47], the switches suffered from low contact conductance. This is potentially caused by the oxidation corrosion and poor step coverage of the aluminum coating. To solve this problem, we conducted gold evaporation experiment to test the side coating capability of the E-gun evaporating process. The minimum thickness of gold as a conducting material is approximately 200 Å based on empirical data. We examined the devices to determine if the gold coating met our requirement.
Fig. 3.7 is the upper part of a test finger covered by gold. The gold particle can be seen very clearly. The EDS (Energy Dispersive Spectrometer) result at the position indicated in Fig 3.7(b) is shown in Fig 3.8, confirming that the coating material is gold.
(a) (b)
Fig. 3.7 (a) Upper part of a gold coated test finger, (b) close-up view
Fig 3.8 EDS result at square in Fig 3.7(b)
Fig 3.9 shows the cross section of the upper test structure. The thickness of gold on the side wall is approximately 0.3 μm which is larger than the 200Å requirement.
The EDS result in Fig 3.10 shows the exposed area is silicon as we expected.
(a) (b) Fig. 3.9 (a) Cross section of test structure, (b) close-up view
Fig 3.10 EDS result at square in Fig 3.9(b)
Fig 3.11 shows the cross sectional view of the test structure 130 μm below the substrate surface. In the high resolution SEM photo we can still see the gold particle clearly as shown in Fig 3.11 (c). However, the wavelike etching profile of the deep ICP etching causes difficulty to determine the actual thickness of deposited gold. The EDS result in Fig 3.12 shows the side wall gold coating density is less than the upper part. Fortunately, the gold deposited on the upper part of the sidewall is acceptable as a contact material.
130μm 130μm
(a) (b)
(c) (d)
Fig 3.11 (a) Cross section view of test structure, (b) close-up view 130 μm below substrate surface, (c) gold particles on wavelike etching profile, (d) wavelike etching profile.
In this improved coating process, the coverage of evaporated gold is good enough to achieve the contact requirement from the above measured results. The stability of gold is also far more superior to aluminum. Table 3.2 summarizes the EDS results of the sidewall coating.
Table 3.2 Element percentage at upper and lower part of sidewall
Depth 1μm 130μm
Au 88.24% 62.10%
Si 4.05% 35.62%
Others <8% <3%
3.3 Fabricated device
A fabricated die is shown in Fig. 3.13. The central hole is used to mount the external mass in order to adjust the resonant frequency to the design specification.
The fingers and serpentine springs are shown in Fig. 3.14. The depth and width of these structures are 200 μm and 10 μm, respectively. In order to yield the ideal finger width of 10 μm, the width on the mask should be pre-enlarged to 13 μm to compensate for the dimension shrinkage during the photolithography and ICP processes. Switch 1 and Switch 2 are shown in Fig. 3.15 and Fig 3.16. We can notice that gold is successfully deposited on the sidewall of the contact region in Switch1 and Switch2, as we expected in Section 3.2.
(a) (b) Fig. 3.13 (a) Fabricated die, (b) central hole for mounting the external mass
(a) (b) Fig. 3.14 Close-up view of (a) fingers, (b) serpentine spring
(a) (b)
(a) (b) Fig. 3.16 (a) Top view of Switch 2, (b) close-up view of Switch 2
The backside of the device was also inspected. Fig. 3.17 shows the backside under Switch 1. The purpose to remove the backside silicon is to reduce parasitic capacitance between the moving plate and the substrate. The backside hole can also eliminate the electrical leakage problem of Switch 1 after metal deposition.
(a) (b)
Fig. 3.17 (a) Backside silicon removed under Switch 1 (b) close-up view
Fig. 3.18 shows the optical micrograph of the device with LPCVD silicon nitride coated on the fingers. The vertical line in Fig. 3.19 is the boundary between silicon and nitride after the frontside nitride is removed. It is caused by the rugged
Silicon nitride coating
Silicon nitride coating