In this chapter, the surface micromachining-like fabrication process for the proposed device, which integrates the SOI wafer and the SU-8 photoresist, is described. The related process parameters are also presented. Finally, the encountered problems during fabrication are discussed.
3-1 Integration of SOI and SU-8
Flatness is an important requirement for optical devices. The SOI wafers are used due to its flat surface characteristic. Using SOI wafers also can simplify the process flow. SU-8 has good mechanical property and low process temperature.
Therefore, the proposed device was fabricated by combining SOI wafers with SU-8.
Table 3-1 is a brief comparison between the common surface micromachining fabrication technology and the proposed SOI with SU-8 fabrication process. The advantages of low process temperature and structure flatness make the SOI with SU-8 process much more suitable for optical applications compared with the general surface micromachining fabrication.
Structural layers Process
temperature
Structure flatness
Process complexity
MUMPs Polysilicon High Low High
SOI+polysilicon SCS and polysilicon High High High
SOI+SU-8 SCS and SU-8 Low High Low
Table 3-1 Comparison of process
SOI Substrate
BOX SCS layer SU-8 photoresist photoesist 90° optical plate (SCS material)
SU-8 hinge Hinge pin
Backside cavity
SCS layer
BOX
Push pad
Figure 3-1 Schematic of a 90° micromirror.
SOI substrate
Figure 3-1 is the cross-section view of a 90° micromirror fabricated using this process. The detailed process flow and parameters will be discussed in the following sections.
3-2 Process Flow
The fabrication process for the proposed micromirror device is illustrated in Figure 3-2. Most fabrication processes were performed in the Nano Facility Center at National Chiao Tung University. The detailed process descriptions and parameters are presented as following.
Step A: SOI starting wafer
The process started with a SOI wafer, as shown in Figure 3-2 (1). The SOI specification is listed in the following.
Diameter 100 ± 0.1 mm Device layer 5 ± 0.5 μm BOX thickness 2 μm ± 5%
Handle layer 400 ± 10 μm
Step B: Wafer cleaning
First of all, a standard RCA clean process was performed on the bare SOI wafer. The purpose of this process is to remove contaminants on the surface of the wafer. Contamination results in reduced component service life, degraded performance characteristics and reduced reliability. The detailed RCA clean flow can be found in [32].
Step C: Backside oxide deposition
PECVD was utilized to deposit 3μm-thick silicon oxide on the backside of the wafer, as shown in Figure 3-2 (2). This oxide layer was used as a hard mask in a later ICP process. The process parameters are listed in the following.
SiH4 flow rate 5 sccm N2O flow rate 90 sccm Process pressure 400 mtorr Process temperature 350 °C
RF power 10 W
Deposition time 45 min.
Step D: Photolithography process – optical frame structure definition (Mask1)
Mask1 defines the optical frame structures in the 5 μm thick layer. The SCS layer was etched with a photoresist mask by ICP. FH6400 positive photoresist was selected as the mask material. The process parameters are listed in the following.
HMDS priming Vapor prime oven
Spin coating Spread speed = 1000 rpm for 10 sec.
Spin speed =2000 rpm for 35 sec.
Soft bake 90 °C hotplate for 150 sec.
Alignment Karl Suss MA6 mask aligner
Exposure 90 sec
Development Developer FHD-5 for 1 min.
Rinse DI water for 1 min.
Hard bake 120 °C hotplate for 30 min.
Step E: ICP etching
ICP DRIE was used to anisotropically etch the 5 μm thick device layer of the SOI wafer, as shown in Figure 3-2 (3). The ICP process was done by the ICP etching service of ITRC (Instrument Technology Research Center).
Step F: Photolithography process – anchor definition (Mask2)
Mask2 is used to define the anchor positions. The 2 μm thick BOX of the SOI wafer was etched using RIE. AZ4620 photoresist was used as the RIE mask.
The process parameters are listed in the following.
HMDS priming Vapor prime oven
Spin coating Spread speed = 1000 rpm for 10 sec.
Spin speed =2500 rpm for 30 sec.
Soft bake 90 °C hotplate for 20 min.
Alignment Karl Suss MA6 mask aligner
Exposure 350 sec.
Development Developer AZ-300 for 4 min. 35 sec.
Rinse DI water for 1 min.
Hard bake 120 °C hotplate for 60 min.
Step G: Reactive ion etching
The SAMCO RIE-10N etcher was used to remove the BOX layer which was not cover by the photoresist mask. The etching depth was 2 μm, as shown in Figure 3-2 (4). The following shows the RIE parameters.
SF6 flow rate 30 sccm CHF3 flow rate 10 sccm Helium back side cooling 15 sccm Process pressure 50 mtorr
RF power 100 W
Etch time 22 min.
Step H: Oxide deposition
A 3 μm thick SiO2 was deposited by PECVD on the top side of the SOI wafer.
This 3μm thick PECVD oxide layer and 2μm thick BOX layer of SOI were used as a sacrificial layer for the free rotation space in the anchor. The process parameters are the same as used in Step C.
Step I: Photolithography process – anchor definition (Mask2)
Mask2 was used again to define the anchor positions. The 3μm thick SiO2
deposited in Step H was etched using RIE etcher. AZ4620 photoresist was used as the mask. The photolithography process parameters are listed in the following.
HMDS priming Vapor prime oven
Spin coating Spread speed = 1000 rpm for 10 sec.
Spin speed =2000 rpm for 30 sec.
Soft bake 90 °C hotplate for 30 min.
Alignment Karl Suss MA6 mask aligner
Exposure 350 sec.
Development Developer AZ-300 for 4 min. 35 sec.
Rinse DI water for 1 min.
Hard bake 120 °C hotplate for 60 min.
Step J: Reactive ion etching
As shown in Figure 3-2 (5), the 3μm thick oxide was etched with the following RIE parameters.
SF6 flow rate 30 sccm CHF3 flow rate 10 sccm Helium back side cooling 15 sccm Process pressure 50 mtorr
RF power 100 W
Etch time 32 min.
Step K: SU-8 photolithography process – latch and hinge definition (Mask3)
Mask3 defined the side latch structures and the hinge elements, as shown in Figure 3-2 (6). These structures were made of 13-μm-thick SU-8 negative photoresist. The SU-8 process parameters are listed in the following.
Dehydration bake 120 °C hotplate for 30min.
Spin coating Spread speed = 500 rpm for 10 sec.
Spin speed =3000 rpm for 30 sec.
Pre-bake 65 °C hotplate for 1 min.
Soft bake 95 °C hotplate for 2 min.
Alignment K-310P-100S
Exposure 4 sec.
Post-exposure bake 65 °C hotplate for 1 min.
95 °C hotplate for 2 min.
Development SU-8 Developer for 3 min.
Rinse IPA for 1 min
Hard bake 200 °C hotplate for 20 min.
Step L: Double side photolithography process – backside cavity definition (Mask4) Mask4 defined the backside cavity of the substrate which was as a room for the assembly procedure. The oxide layer deposited in Step C, which was used as an ICP mask, was etched by RIE with photoresist AZ4620 mask. The photolithography parameters are listed in the following.
HMDS priming Vapor prime oven
Spin coating Spread speed = 1000 rpm for 10 sec.
Spin speed =2000 rpm for 40 sec.
Soft bake 90 °C hotplate for 25 min.
Alignment EV620 mask aligner
Exposure 12 sec.
Development Developer EDP-1000 for 1 min. 10 sec.
Rinse DI water for 1min.
Hard bake 120 °C hotplate for 60 min.
Step M: Reactive ion etching
As shown in Figure 3-2 (7), the 3μm thick backside oxide was etched with the RIE parameters as described in Step J.
Step N: ICP etching
The 400μm thick substrate of the SOI wafer was etched by ICP, as shown in Figure 3-2 (8). Oxide was chosen as the ICP mask instead of the photoresist due to the higher ICP selectivity of silicon to SiO2 compared to that of silicon to photoresist. The thick etching depth, 400 μm in this case, needs a thick photoresist as mask. This will increase the process complexity. Another reason is the photoresist may be burned during the long ICP process time. This will result in destroyed patterns. The backside ICP process was done by the ICP etching service of C SUM MFG. Ltd.
SOI Substrate
SOI Substrate
BOX SCS layer PECVD Oxide
SOI Substrate
BOX SCS layer
BOX SCS layer
(2) Backside oxide deposition (Step C) Step O: Oxide release
The devices were released when the sacrificial oxide layer was removed by 49% HF solution and rinsed in IPA for 10 minutes, as shown in Figure 3-2 (9).
Step P: Micromanipulator assembly
Finally, the released microstructures were manually assembled using micromanipulator station, as illustrated in Figure 3-2 (10).
(1) SOI wafer cleaning (Step A, Step B)
PECVD Oxide
SOI Substrate
PECVD Oxide
SOI Substrate
BOX SCS layer PECVD oxide
SOI Substrate SCS layer
BOX SCS layer
(4) Anchor patterning (Step F, Step G)
(5) Anchor patterning (Step H, Step I, Step J) SOI Substrate
(6) SU-8 patterning (Step K)
SCS layer SU-8 photoresist
photoresist
(7) Backside oxide patterning (Step L, Step M)
PECVD oxide
SU-8 photoresist
PECVD oxide BOX
BOX
Figure 3-2 Fabrication process of the proposed device (continued).
SOI Substrate
BOX SCS layer
SOI Substrate
BOX SCS layer SU-8 photoresist photoresist PECVD oxide SU-8 photoresist photoresist
(8) Backside ICP etching (Step N)
SOI Substrate
BOX SCS layer SU-8 photoresist photoesist (10) Microprobe assembly (Step P)
(9) Oxide release (Step O)
Microprobe
Figure 3-3 Photographs of the device structures during the fabrication processes.
The photographs of the device structures during the fabrication processes are presented in Figure 3-3. Figure 3-3 (a) and Figure 3-3 (b) show the minimum feature size (5 μm hinge pin) was defined after frontside ICP. The SU-8 V-shaped hinge and side latch structures were well patterned as shown in Figure 3-3 (c) and Figure 3-3 (d).
The released structures shown in Figure 3-3 (e) and Figure 3-3 (f) are mirrors with the push pad and without the push pad, respectively. The mirrors without etch holes after releasing are shown in Figures 3-3 (g)-(j). Figure 3-3 (g) has a backside pattern with a big hole; Figure 3-3 (i) has a silicon pillar array in the backside pattern.
(a) (b)
(c) (d) 5um thick hinge pin
V-shaped hinge
(SU-8) Side latch (SU-8)
Figure 3-3 Photographs of the device structures during the fabrication processes (continued).
(e) (f)
(g) (h)
Backside cavity Push pad
Backside hole
(i) (j) Backside
pillar
Mirror plate without etch holes Mirror plate without etch holes
3-3 Fabrication problems and discussions
Two potential problems with the fabrication process are SU-8 adhesion and stiction. The adhesion strength of SU-8 to silicon is susceptible to fabrication parameters. The stiction between large mirror plate and substrate causes the assembly failure. The solutions to address these problems are discussed and presented in following sections.
3-3-1 Adhesion of SU-8 structures
During the SU-8 related process steps, the adhesion strength of the SU-8 structures to the silicon substrate may be weak. This can cause the SU-8 layer to peel off during the fabrication or operation. Figure 3-4 shows that a weak SU-8 anchor peeled off during the assembly process. In order to enhance the adhesion of SU-8 to the substrate, the process parameters are modified.
From [33-34], the adhesion of SU-8 to silicon can be easily affected by substrate cleanness and process parameters. The silicon wafer surface has to be extremely dry and clean. Peeling can also happen in the presence of a native oxide layer on the silicon before SU-8 coating. The SU-8 curing parameters are another important factor for adhesion failure. Slow ramping of the curing temperature is needed in order to improve the substrate adhesion. Accordingly, the process parameters of the SU-8 are modified as in Table 3-2, obeying the following rules,
1. Dry and clean silicon substrate is critical.
2. Native silicon oxide is removed before SU-8 coating.
3. Slow ramping of the SU-8 curing temperature is very important to enhance adhesion.
Step Parameter Comment
HF dip 100:1 HF dip 10 sec. HF dips to remove native oxide layer prior to SU-8 deposition.
Dehydration bake
150 °C hotplate for 20 min, Dry substrate is necessary.
Spin coating Spread speed
= 500 rpm for 10 sec.
(1) Curing temperature with slow ramping is very important to adhesion. (2) Slow cooling ramping is also required.
Alignment K-310P-100S
Exposure 4 sec.
(1) Curing temperature with slow ramping is very important to adhesion. (2) Slow cooling ramping is also required.
Table 3-2 Modified SU-8 parameters
Figure 3-4 (a) The mirror plate is lifted by a probe, (b) as the plate is lifted further, the weak SU-8 anchor is detached.
(a) (b)
The adhesion of SU-8 structures fabricated with the modified parameters are studied and analyzed in the following experiments. First, the adhesion problem is analyzed by the occurrence percentage of delamination in all processed SU-8 structures. Second, SU-8 spring structures are randomly pulled and intentionally broken using microprobes. It is recorded whether the SU-8 spring structures peel off before breaking. If the anchor area of the SU-8 spring is not detached before breaking, it means the SU-8 adhesion is strong enough. Figure 3-5 shows the micrographs of the experimental process. The SU-8 was pulled and broken by using a microprobe as shown in Figures 3-5 (a)-(c). Figure 3-5 (d) shows that the SU-8 anchor was still well in place even the spring was broken. There were totally 361 fabricated SU-8 samples.
86 samples were randomly selected for test. Experimental results show that the delamination of SU-8 anchors after release is zero among the 86 samples. The number of detached SU-8 anchors after breaking was 5. Therefore the failure rate is only 6%.
Figure 3-5 Experimental process of SU-8 adhesion test.
(a) (b)
(c) (d) SU-8 is not detached
Breaking point
3-3-2 Vapor HF release
The final step in the fabrication process is to release the microstructure from the sacrificial oxide layer. When an aqueous HF solution is used for the release process, the surface tension can pull two structures together and result in the stiction of suspended structures to the substrate after rinsing in DI water or IPA. This stiction phenomenon can significantly reduce yield. As shown in Figure 3-6, the assembly process failed due to the stiction between large mirror plate and substrate. The mirror plate was not lifted as the pad was pushed down (Figure 3-6 (b)). The pad was broken as it was pushed further (Figures 3-6 (c), (d)). Vapor phase etching is a promising solution to address the stiction problem because it avoids the wet etching and rinsing steps. Hence the modified release process uses vapor HF to etch the oxide layer.
Nevertheless, the vapor HF technique usually needs complicated apparatus. In this thesis, a simple method proposed by [35] was adopted for vapor HF releasing.
(a) (b) The mirror plate was stationary
Figure 3-7 schematically illustrates the experimental setup of the vapor HF process. This system consists of two Teflon dishes, one plastic film, and one light bulb.
First, liquid HF was poured into a Teflon beaker. Then the Teflon beaker was covered with a plastic film. The chip is placed on this plastic film with holes to ensure the HF vapor can pass through to the chip. Another Teflon dish caps the HF vessel to keep the HF vapor inside and avoids any leakage. The light bulb is used to warm up the chip and to control the temperature during the process. Figure 3-8 shows the setup used in this thesis. Obviously, these components are very cheap and simple; no complicated apparatus is necessary.
Light bulb
Teflon dishes
Plastic film
Liquid HF Silicon chip
Figure 3-7 Schematic illustration of a vapor HF release apparatus. The chip is placed on a plastic film.
3-4 Fabricated structure
Figure 3-9 shows the SEM photographs of the device after assembly. Figure 3-9 (a) shows an array of the assembled mirrors. Figure 3-9 (b) is the mirror without the push pad and with the V-shaped hinges. Figure 3-9 (c) shows the mirror with the push pad and V-shaped hinges. Figure 3-9 (d) is the mirror without the etch holes and with conventional hinges. Figures 3-9 (e) and (f) are the close-up view of the V-shaped hinge and the cross-section view of the mirror, respectively. The assembly experiment will be discussed in Chapter4.
Figure 3-8 Vapor HF setup used in this thesis.
Light bulb
Teflon dishes Plastic film
(a) (b)
(c) (d)
(e) (f) Figure 3-9 SEM photographs of assembled devices.
V-shaped Hinge (SU-8)
Flexible side latch (SU-8)
V-shaped
Hinge Backside cavity Mirror without etch holes
Conventional hinge
Backside hole V-shaped hinge (SU-8)
3-5 Summary
The SU-8 adhesion and stiction problems can be improved by modified fabrication parameters and vapor HF release, respectively. The SEM photographs of assembled devices indicate the feasibility of the proposed assembly process. In the following chapter, the assembly experiment will be discussed.