We implement the analysis bank filter bank of our multirate architecture. Figure 4-1 shows the analysis bank multirate filter bank is folded into a set of hardware that contains F37 ~ F39, D, and a two times down-sampler.
Figure 4-1 Folded architecture
In the recursive filter bank, the inputs of the filters are coming from outside or the decimation output. The output of F37 ~ F39 may pass a de-multiplexer because the output contains F22 ~ F39’s output. We schedule the folded recursive filter bank by using recursive pyramid algorithm (RPA). The recursive pyramid algorithm is a reformulation of the classical pyramid algorithm (PA) for computing the multi-resolution system, like discrete wavelet transform (DWT). The algorithm is derived because some transformation can be viewed as multi-resolution representation of a sequence X(n) with N/2 values at highest resolution, N/4 values at the next resolution, and so on. The only one difference between the DWT and our multirate filter is that in our multirate system, the sequence X(n) with N values at highest resolution, N/2 values at the next resolution, and so on. In other words, we can follow
the algorithm and make some revises from the RPA algorithm.
In our design, the sixth octave needs to down-sampled by thirty two from the original input so that we can define that thirty two input samples as an execution iteration. Figure 4-2 [19] shows the final schedule of our filter bank for 16 input samples. The numbers that shown in the figure are input sample number. In our multirate filter bank, we must do two octave operations per input sample to meet real time constrain. We do first octave bands for every input sample and do second octave band once for two input sample, and so on. The reason we execute the first octave first is because we should the input data of second to sixth octave’s is ready when executing. Table 4-1 shows the execution timing for details of every octave bands.
The p, q, r, s, t in the table are integers or zero and the period of the input sample is thirty two.
Figure 4-2 RPA scheduling of multirate filter bank
Table 4-1 Execution timing
After scheduling, we implement the design by using a processor-like architecture.
The block diagram of the multirate filter bank is shown in Figure 4-3. In the figure, the engine is a MAC unit (a multiplier and an accumulator). The system control module generates the filters’ status signal like octave number and the executing filter tap to memory control module. The memory control module gets the data input signals and the control signals to determine which input should catch from memory and execute on the MAC module. In the memory, we save filters’ coefficients in ROM and save the inputs on data memory .The mac module executes the F37 ~ F39 and D filters and output the results.
Let us show the details of the modules. The system control module has four signals for executing filters, which are iter, oct, tap, and step. The iter signal is the iteration count that records the first input address of the current executing filter. The oct and tap signals show the executing octave number and the tap of the filters. The step signal is the execution step for each tap. Table 4-2 shows the operations of each tap for system control module. First of all, as we mentioned in Chapter 3, we design all filters by odd taps. In this case, we can easily expand filters’ order of F38, F39, and D to forty one taps by adding zero coefficients on the head and tail coefficients. Take F39 for example, we add zero coefficients on first seven and last seven terms of the
filter so that the F39 becomes forty one taps. When all filters have same taps, we can reduce memory usage by sharing all the inputs. Then we utilize the coefficients symmetric property to reduce half of the multiplications so that filters’ executions are done only by twenty one taps. From Table 4-2, each tap has six steps to execute except some special taps. The special taps are first and last tap because the two taps need to save the data input or the decimation output. Besides, there is only one load operation when tap = 20. The other taps goes from step = 0 to step = 5 that load two data inputs and then load four coefficients. Step = 7 is an extra step that use for synchronization.
Figure 4-3 Filter bank block diagram
Table 4-2 Operations on each tap in system control module
enq sync 7
store fd and enq f37~f39 6
load x(n-tap), or store din 1
store fd and enq f37~f39 6
load x(n-tap), or store din 1
load x(n-(40-tap)) 0
operation step
Furthermore, the system control module also has three control signals for controlling the data. The rdy_in signal is equal to one means the input is ready and we can start to get input and execute the filter bank. After getting input into the filter bank, the enq signal raises to one for a cycle and the rdy_in falls to zero until the next input get ready. The rdy_out signal is similar to rdy_in signal. The rdy_out signal is zero when the output buffer is empty and we can deliver filters’ outputs to the buffer. The rdy_in and rdy_out in system control module play an important role by their interlock mechanism that shown in Figure 4-4.
Figure 4-4 Interlock mechanism (a) input (b) output
For MAC module, the inputs come according to the system control that has
shown above. In our design, we pipeline the step signal to the MAC module such that the MAC module knows the data content that comes from memory. Table 4-3 shows the operations in MAC module. The step_pipe2 signal is the pipeline signal of the step signal. The main function in the MAC module is to perform accumulations of the four filters. The tmp signal is a 17-bit register that store the input data. There are four 31-bit accumulator registers, accd, acc39, acc38, and acc37, storing four filters’
temperature outputs. When the filters’ operations are done, we output the first 16-bit of the accumulator registers acc37 ~ acc39 and decide whether the decimation output accd should save in the memory or not.
Table 4-3 Operations in mac module
acc39+=tmp*h39(tap)