After the LP has been solved, the routes are retrieved by reversely converting the solution from values to points. Regardless of all the efforts, some final tunes might need to get rid of those variations. These adjustments are performed locally by adding bumps around those shorter wires. The routing priority acquired in topology routing can be reused here. By negating routing order, the nets will be tuned from the inner most to outer most. This is reasonable and intuitive; those inner nets have lesser routing around them, serving them first could prevent other nets from occupying these critical regions.
Chapter 5
Experiment Results
We have implemented our methodology in C++ on a machine of quad Intel Xeon CPUs cores with 32GB memory. Also, several cases shown in references (Test Cases I and II resemble the cases shown in [14] since the cases in [14] are not available;
Test Cases III to V are from [?], provided from design houses) are served as our benchmark. Table 5.1 exhibits the test cases and run time for our router. N ets and Component indicate the number of nets and components in test cases. Grid size shows the size (the number of grid cell on PCB board)1 of the routing problem, T otal T ime includes the time for building the routing grid and the run time spent by our router.
Fig. 5.1 shows the Test Case I which has five components. The routing result
1The grid sizes of the test cases in this work are larger than the BSG grid sizes in [14], which shows the granularity of our approach.
Table 5.1: The summary of test cases and experimental results.
#Nets #Components Grid size Total Time
Test Case I 17 5 250× 250 < 1 sec
Test Case II 18 4 300× 230 < 1 sec
Test Case III 57 5 300× 230 < 1 sec
Test Case IV 81 8 640× 560 2sec
Test Case V 104 9 900× 900 2sec
Figure 5.1: The routing result of Test Case I. The result shows that the routing nets are centralized as buses and the routing area is better utilized. The numbers beside pins are the routing order automatically figured out by our topology router.
Figure 5.2: The routing result of Test Case I with our own implementation of work [14].
is quite different from that of [14] as can be seen in Fig.5.1 and Fig.5.2 2. The run times can not be compared fairly for some efficiency considerations, e.g. variables reduction, proposed in that work are not fully implemented in our reimplement ver-sion. Comparison of the results show that almost all nets are routed in certain region
2They compete in same wire space with identical LP solver. BSG grid size is determined dynamically according to topology as described in this work.
_1
_BP:6_BO:5_BN:4_BM:3_BL:2_BK:1_BJ:1_BI:2_BH:3_BG:4_BF:5_BE:6_BD:7_BC:8_BB:9_BA:10_AZ:11_AY:12_AX:13_AW:14 _AF:9
_CL:6_CK:5_CJ:4_CI:3_CH:2_CG:1_CF:1_CE:2_CD:3_CC:4_CB:5_CA:6
_7
_BZ:2_BY:1_BX:1_BW:2_BV:3_BU:4_BT:5_BS:6_BR:7_BQ:8
_1
Figure 5.3: The routing result of Test Case IV. This case has eight components and the length constraints are conformed.
and the routing area is better utilized in our work. On the other hand, controlled by the solver, there is no neat workaround to prevent those unnecessary snaking in Fig. 5.2, and those irregular routing shape might result in certain undesired effects under electromagnetic verification.
Fig. 5.3 shows Test Case IV which has more components than the case in Fig. 5.1.
The net distribution between each component are similar to the result of bus routing.
Our router can also detour the nets to avoid crossing and conform with the length constraints. The top-left enlarged view shows our router can shift the nets in a certain region to meet the length constraints. Moreover, many net-joggings are avoided due to non-floorplan-based approach (area sizing). Even the components
are not face to face, our router can still find a good solution.
Chapter 6 Conclusion
In this work, we have proposed a board routing solution for a practical preas-signed boundary pins problem. Instead of applying the shortest path algorithms like conventional routers, we have discovered some special properties of component and pins from cases and successfully utilized them into our work. Our approach is good in space management, and has the ability to meet the wire length and shape re-quirements at the same time. The experimental results show our work can preserve routing space in sequential planar routing under given boundary pins and conform with the length constraints.
Bibliography
[1] W. M. Dai, T. Dayan, and D. Staepelaere. “Topological Routing in SURF:
Generating a Rubber-Band Sketch”. In Proceedings of ACM/IEEE Design Automation Conference, pages 39–44, 1991.
[2] Z. Dong and M. Li. “A Routing Method of Ad Hoc Networks Based on A-star Algorithm”. In International Conference on Networks Security, Wireless Communications and Trusted Computing, pages 623–626, 2009.
[3] H. Kong, T. Yan, and D. F. Wong. “Automatic Bus Planner for Dense PCBs”.
In Proceedings of ACM/IEEE Design Automation Conference, pages 326–331, 2009.
[4] H. Kong, T. Yan, and D. F. Wong. “Optimal Simultaneous Pin Assignment and Escape Routing for Dense PCBs”. In Proceedings of IEEE Asia and South Pacific Design Automation Conference, pages 275–280, 2010.
[5] Y. Kubo, H. Miyashita, Y. Kajitani, and K. Tateishi. “Equidistance Rout-ing in High-Speed VLSI Layout Design”. In ProceedRout-ings of the Great Lakes Symposium on VLSI, pages 439–449, 2005.
[6] L. Luo and M. Wong. “Ordered Escape Routing Based on Boolean Satisfia-bility”. In Proceedings of IEEE Asia and South Pacific Design Automation Conference, pages 244–249, 2008.
[7] L. Luo, T. Yan, Q. Ma, D. F. Wong, and T. Shibuya. “B-Escape: A Simultane-ous Escape Routing Algorithm Based on Boundary Routing”. In Proceedings of ACM International Symposium on Physical Design, pages 19–25, 2010.
[8] Q. Ma, T. Yan, and M. Wong. “A Negotiated Congestion based Router for Simultaneous Escape Routing”. In Proceedings of International Symposium on Quality Electronic Design, pages 606–610, 2010.
[9] M. M. Ozdal and D. F. Wong. “Simultaneous Escape Routing and Layer As-signment for Dense PCBs”. In Proceedings of ACM/IEEE Design Automation Conference, pages 822–829, 2004.
[10] M. M. Ozdal and D. F. Wong. “Algorithmic Study of Single-Layer Bus Routing for High-Speed Boards ”. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 25, pages 490–503, Mar. 2006.
[11] M. M. Ozdal and D. F. Wong. “Two-Layer Bus Routing for High-Speed Printed Circuit Boards”. In ACM Transactions on Design Automation of Electronic Systems, volume 11, pages 213–227, Jan. 2006.
[12] M. M. Ozdal, D. F. Wong, and P. S. Honsinger. “An Escape Routing Framework for Dense Boards with High-Speed Design Constraints”. In Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pages 759–
766, 2005.
[13] M. M. Ozdal, D. F. Wong, and P. S. Honsinger. “Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards”. In IEEE Transac-tions on Computer-Aided Design of Integrated Circuits and Systems, volume 27, pages 84–95, Jan. 2008.
[14] T. Yan and D. F. Wong. “BSG-Route: A Length-Matching Router for Gen-eral Topology”. In Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pages 499–505, 2008.
[15] T. Yan and D. F. Wong. “A Correct Network Flow Model for Escape Routing”.
In Proceedings of ACM/IEEE Design Automation Conference, pages 332–335, 2009.
[16] M. F. Yu and W. M. Dai. “Single-Layer Fanout Routing and Routability Anal-ysis for Ball Grid Arrays”. In Proceedings of IEEE/ACM International Con-ference on Computer-Aided Design, pages 581–586, 1995.
[17] K. J. Supowit. “Finding a Maximum Planar Subset of a Set of Nets in A Channel”. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 6, pages 93–94, Jan. 1987.
[18] T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein. “Introduction to Algorithms”. Second edition, Page 350–355.
[19] F. Nicolas and E. Rivals. “Longest Common Subsequence Problem for Un-oriented and Cyclic Strings”. In Journal Theoretical Computer Science, vol-ume 370, Issue 1–3, Page 1–18, 2007.
[20] T. Y. Tsai, R. J. Lee, C. Y. Chin, C. Y. Kuan, H. M. Chen, and Y. Kajitani “On Routing Fixed Escaped Boundary Pins for High Speed Boards”. In Proceedings of the Design Automation and Test in Europe Conference and Exhibition, Page 1–6, Mar. 14-18, 2011.