The techniques presented here for deciding the significant factors in RIE process are general in the sense and can be applied to many other plasma environments process.
Moreover, this methodology can also be applied to other semiconductor equipment to find the significant factors.
The best performance of prediction models has been achieved by online BPNN prediction model. This model can be further extended to predict the plasma characteristic, etching parameters and other type of defect. The online BPNN performance can be enhanced by implement fast and continuance feedback control.
Statistical summary preparation technique has the potential to meet the prediction models requirements in RIE process. Excellent models could be achieved by implementation the statistical summary preparation technique in multi-step processes.
References:
[1] M. Quirk, and J. Serda, "Semiconductor Manufacturing Technology," Prentice-Hall, New Jersey, pp.435-474, 2001.
[2] E. Mollick, "Establishing Moore's Law," IEEE Annals of the History of Computing, vol. 28, no. 3, pp. 62-75, Jun 1998.
[3] C. Weber, D. Jensen, and E. D. Hirleman, "What Drives Defect Detection Technology?" Micro Magazine, pp. 51-72, June 1998.
[4] SIA Semiconductor Industry Association, "Yield Enhancement," National Technology Roadmap for Semiconductors, 2005 Ed.
[5] C. Weber, "Yield Learning and the Sources of Profitability in Semiconductor Manufacturing And Process Development," IEEE Transactions on Semiconductor Manufacturing, vol. 17, no. 4, pp. 590-596, 2004.
[6] D. Abercrombie, and J. Jahangiri, "Value-Added Defect Testing Techniques,"
IEEE Design & Test of Computers, 2005.
[7] R. J. Shul, and S. J. Pearton, "Handbook of Advanced Plasma Processing Techniques," Springer, New York, 2000.
[8] J. Yi, Y. Sheng, and C. S. Xu, "Neural Network Based Uniformity Profile Control of Linear Chemical Mechanical Planarization," IEEE Transactions on Semiconductor Manufacturing, vol. 16, no. 4, pp. 609-620, 2003.
[9] S. R. Bhatikar, and R. L. Mahajan, "Artificial Neural-Network-Based Diagnosis of CVD Barrel Reactor," IEEE Transactions on Semiconductor Manufacturing, vol. 15, no. 1, pp. 71-78, 2002.
[10] K. L. Hsieh, and L. I. Tong, "Optimization of Multiple Quality Responses Involving Qualitative and Quantitative Characteristics in IC Manufacturing Using Neural Networks," Computers in Industry, vol. 46, pp. 1-12, 2001.
[11] D. Stokes, and G. S. May, "Real-Time Control of Reactive Ion Etching Using Neural Networks", IEEE Transactions on Semiconductor Manufacturing,, vol.
13, no. 4, pp. 469-480, November 2000.
[12] J.-H. Lai, and C.-T. Lin, "Application of Neural Fuzzy Network to Pyrometer Correction and Temperature Control in Rapid Thermal Processing," IEEE Transactions on Fuzzy Systems, vol. 7, no. 2, pp. 160-175, 1999.
[13] B. Kim, and G. S. May, "An Optimal Neural Network Process Model for Plasma Etching," IEEE Transactions on Semiconductor Manufacturing, vol. 7.
no. 1, pp. 160-175, 1994.
[14] F.-L. Chen, and S.-F. Liu, "A neural-network approach to recognize defect spatial pattern in semiconductor fabrication," IEEE Transactions on Semiconductor Manufacturing, vol. 13, no. 3 , pp. 366-373, 2000
[15] J. H. Lee, S. J. You, and S. C. Park, "A New Intelligent SOFM-based Sampling Plan for Advanced Process Control," Expert Systems with Applications, vol. 20, pp. 133-151, 2001.
[16] F.-L. Chen, S.-F. Liu, K. Y.-Y. Doong, and K.L. Young, LOGIC "Product Yield Analysis by Wafer Bin Map Pattern Recognition Supervised Neural Network," IEEE International Symposium on Semiconductor Manufacturing,
vol. 1, pp. 501-504, 2003.
[17] F. Di Palma, G. D. Nicolao, G. Miraglia, E. Pasquinetti, and F. Piccinini,
"Unsupervised Spatial Pattern Classification of Electrical-Wafer-Sorting Maps in Semiconductor Manufacturing," Pattern Recognition Letters, vol. 26, pp.
1857-1865, 2005.
[18] S.S. Han, M. Ceiler, S. A. Bidstrup, P. Kohl, and G. May, "Modeling the Properties of PECVD Silicon Dioxide Films Using Optimized Back Propagation Neural Networks," IEEE Transactions on Components, Packing, and Manufacturing Technology, vol. 17, no. 2, pp. 174-182, 1994.
[19] S. S. Han, and G. S. May, "Using neural network process models to perform PECVD silicon dioxide recipe via genetic algorithms," IEEE Transactions on semiconductor manufacturing, vol. 10, no. 2, pp. 279-287, 1997.
[20] B. Kim, D. W. Kim, and G. T. Park, "Prediction of Plasma Etching Using a Polynomial Neural Network, " IEEE Transactions on Plasma Science, vol. 31, no. 6, pp. 1330-1336, December 2003.
[21] B. Kim, and W. S. Hong, "Use of Neural Network to Characterize a Low Pressure Temperature Effect on Refractive Property of Silicon Nitride Film Deposited by PECVD," IEEE Transactions on Plasma Science, vol.32, no. 1, pp. 84-89, 2004.
[22] D. B. Fogel, "An Information Criterion for Optimal Neural Network Selection," IEEE Transaction on Neural Network, vol. 2, no. 5, pp. 490-497, 1991.
[23] N. Murata, and S. Yoshizawa, "Network Information Criterion-Determining the Number of Hidden Units for an Artificial Neural Network Mmodel," IEEE Transaction on Neural Network, vol. 5, pp. 865- 872, 1994.
[24] T. Onoda, "Neural network information criterion for optimal number of hidden units," Proceedings of the IEEE International Conference on Neural Networks, vol. 1, pp. 270- 280, 1995.
[25] J. F. C. Khaw, B. S. Lim, and L. E. N. Lim, "Optimal Design of Neural Network Using the Taguchi Method," Neurocomputing, vol. 7, pp. 225-245, 1995.
[26] M. S. Santos, and B. Ludermir, "Using Factorial Design to Optimize Neural Networks," International Joint Conference on IEEE Neural Networks, vol. 2, pp. 857-861, 1999.
[27] R. A. Zoroofi, H. Taketani, S. Tamura, Y. Sato, and K. Sekiya, "Automated Inspection of IC Wafer Contamination," Pattern Recognition, vol. 34, pp.
1307-1317, 2001.
[28] C.-T. Su, T. Yang, and C. M. Ke, "A Neural-Network Approach for Semiconductor Wafer Post-Sawing Inspection," IEEE Transactions on Semiconductor Manufacturing, vol. 15, no. 2, pp. 260-266, 2002.
[29] W. C. Chen, C. T. Chen, T. H. Ho, J. H Chen, and L. J. Sheu, "Use of Neural Network in Pattern Recognition of Semiconductor Etching Process," The Proceedings of the 11th International Conference on Industrial Engineering
and Engineering Management, vol. 1, pp. 719-725, 2005.
[30] I. Belic, "Neural Networks and Modelling in Vacuum Science," Vacuum, vol.
80, no. 10, August 3, pp. 1107-1122, 2006.
[31] P. J. Werbos, "The Roots of Back Propagation from Ordered Derivatives to Neural Networks and Political Forecasting," Wiley Interscience, New York, 1994.
[32] K. Y. Huang, "Neural Networks and Pattern Recognition," Hsinchu, Taiwan, 2003.
[33] P. F. Williams, "Plasma Processing of Semiconductors," NATO ASI Series, vol. 336, Kluwer Academic Publishers, London, 1997.
[34] J. P. Chang and J. W. Coburn, "Plasma-surface interactions," Journal of Vacuum Science and Technology vol. 21, pp. 145-151, 2003.
[35] P. F. Williams, "Plasma Processing of Semiconductors," NATO ASI Series, Vol. 336, Kluwer Academic Publishers, London, 1997.
[36] K. Pearson, "On Lines and Planes of Closest Fit to Systems of Points in Space,
" Philosophical Magazine vol. 2, pp. 559–572, 1901.
[37] H. Hotelling, "Analysis of a Complex of Statistical Variables into Principal Components," Journal of Educational Psychology vol. 24, pp. 417–441, 1933.
A PPENDIX I
T ERMINOLOGY
Critical Dimension CD. The width of a patterned line or the distance between two lines of the sub-micron sized circuits in a chip.
Dielectric A material that conducts no current when it has a voltage across it; an insulator. Two dielectrics commonly used in semiconductor processing are silicon dioxide (SiO2) and silicon nitride (SiN).
Drift A change of a reading or a set point value over long periods due to several factors including change in ambient temperature, time, and line voltage
Electrostatic Chuck Lower plate in a chamber that holds wafers using electrostatic attraction, allowing the temperature to be regulated with confined helium gas. Different types of ESC include bipolar designs based on dual electrodes in the chuck and monopolar chucks with a single electrode. Plasma gas that comes in contact with the wafer provides the other electrode in the circuit that clamps the wafer in place. Also called a chiller plate (temperature typically = 15 C).
Etch A solution, a mixture of solutions, or a mixture of gases that attacks the surfaces of a film or substrate, removing material
either selectively or non-selectively.
FAB Semiconductor fabrication facility. Under precise conditions, silicon or other semiconductor materials are transformed along with other basic elements into semiconductors, or microchips.
In situ In the natural or original position or place. For SensArray, this means performing tests in or on the actual device (process chamber, hotplate, etc.) that will be used to produce the end product. This provides real world data as to the characteristics of the device.
Insulator Nonconductive dielectric films used to isolate electrically active areas of the device or chip from one another. Some commonly used insulators are silicon dioxide, silicon nitride, boro-phospho-silicate glass (BPSG), and phospho-boro-phospho-silicate glass (PSG).
Ion Implantation A process technology in which ions of dopant chemicals (boron, arsenic, etc.) are accelerated in intense electrical fields to penetrate the surface of a wafer, thus changing the electrical characteristics of the material.
Load Lock An isolation chamber that allows a process chamber to be protected from ambient conditions.
Metallization The deposition of a layer of high-conductivity metal such as aluminum used to interconnect devices on a chip by CVD or PVD. Metals typically used include aluminum, tungsten, and copper.
Photo-resist A light-sensitive organic polymer that is exposed by the photolithography process, then developed to produce a pattern which identifies areas of the film to be etched.
Plasma Ionized gases that have been highly energized-for example, by a radio frequency energy field. This can be used to remove resist, to etch, or to deposit various layers onto a wafer.
Plasma-Enhanced TEOS Oxide Deposition
A deposition process in which tetraethoxysilane (TEOS) is used as a silicon source to deposit silicon dioxide on a wafer surface.
Polysilicon (Poly) Polycrystalline silicon; extensively used as conductor/gate material in a highly doped state. Poly films are typically deposited using high-temperature CVD technology.
Process Chamber An enclosed area in which a process-specific function occurs during wafer manufacturing.
PVD Physical Vapor Deposition (also called sputtering). A process technology in which molecules of conducting material (aluminum, titanium nitride, etc.) are "sputtered" from a target of pure material, then deposited on the wafer to create the conducting circuitry within the chip.
RIE Reactive Ion Etch. A combination of chemical and physical etch processes using electrical discharge to ionize and induce ion bombardment of the wafer surface to obtain the required etch properties.
Short Term Drift A change in the temperature reading of the sensor(s) at a fixed ambient reference temperature over short periods of time. Usually expressed as degrees C change per hour.
Silicon (Si) A brownish crystalline semimetal used to make the majority of semiconductor wafers.
Silicon
Dioxide(SiO2)
A passivation layer thermally grown or deposited on wafers. It is resistant to high temperatures. Oxygen or water vapor is used to grow silicon dioxide at temperatures above 90 C. Silicon dioxide is used as a masking layer as well as an insulator.
Stepper Equipment used to transfer a reticle (mask) pattern onto a wafer.
Substrate A material that is the basis for subsequent processing operations in the fabrication of semiconductor devices or circuits. Examples of a substrate would include a silicon wafer or a glass panel.
Test Wafer A wafer used for process monitoring during semiconductor manufacturing. The two types are the reclaim test wafer and the virgin test wafer. With test wafers you are looking at some telltale indication of differences in film thickness, a change in resistance in material, the width of a line, or a feature (critical dimension) due to changes in the temperature of the wafer.
Wafer The thin, circular slice with parallel faces of pure silicon cut from a semiconductor crystal on which semiconductors are built.
Yield The percentage of wafers or die produced in a process that
conform to specifications.
A PPENDIX II P RINCIPAL C OMPONENT S CORES
First Step
T1=5.86708E-05* X1+0.546231739* X2+0.459104457* X3-0.687346122* X4+ 0.120997137*X5-
0.018545951*X16+0.000904692*X17+0.014537893*X18+0.045280312*X19+0.006767968*X20-T3
T1=0.365956063*X1+0.084013161*X2+0.924990635*X3-0.034408355*X4-0.031511413*X5+
=-0.279000558*X1+0.911324425*X2+0.091455252*X3-0.109681988*X4-0.027038587*X5-
0.001068294*X16-0.030158155*X17-0.04114025*X18+0.151297081*X19-0.687159832*X20+