Future Work

Future works are formed by three parts. First is about the coding efficiency. From proposed FGBPZ to CGBPZ, we made a trade off between the encoding/decoding cycles and the visual quality. CGBPZ achieves fast coding speed and acceptable

visual quality. However, error propagation delivered through 29 P frames is still noticeable by human eyes. To embed a compressor/decompressor in video decoder, the only way to get better visual quality is to reduce the quality loss of each referred frame. Therefore, refine coding scheme to reduce quality loss is very importance.

Second part is to develop adaptive compensation modes according to different characteristics of video sequences. The compensation method we proposed is based on universal behaviors of our testing data base. Proposed compensation method reaches minimum average PSNR loss over our data base. But we also found other kinds of methods have better performance on compensating certain video sequences while having poor performance on the others. That is why we wish to develop adaptive compensation modes. To compensate sequences according to their characteristics can optimal the individual visual quality and is also a direction of quality improvement. Since the power consumption of our embedded codec is much less than the power we reduced on access reduction, to increase reasonable complexity to get better performance is a good idea and is worth us to try.

The final part is about the memory power model. The memory power model we use is to estimate the memory power consumption according to the average behavior of data access ratio [21]. For a detail analysis, there are some factors needed to be specified such as page mode design and burst length. The burst length determines the efficiency of memory data read accesses and page mode determinates the hit rate.

Power consumption on memory is related to those factors. If we can build a power model taking those factors into account, we can analyze our memory power consumption in a more accurate way.

References

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[20] Chieh-Hsien Cheng, “An Embedded Compressor/De-compressor for Video Decoder Using VQ/DCT Hybrid Coding”, master thesis, 2007

[21] Micron® Technology Inc. The Micron® System-Power Calculator: SDRAM.

[Online Available]: http://www.micron.com/products/dram/syscalc.html

[22] Micron® Technology Inc. MT48LC2M32B2 64Mb SDRAM. [Online Available]:

http://www.micron.com/products/dram/

作 者 簡 歷

姓名 ：吳昱德

戶籍地 ：台灣省台中市 出生日期：1984. 02. 01

學歷： 1999. 09 ~ 2002. 06 國立台中第一高級中學

2002. 09 ~ 2006. 06 國立交通大學 電子工程學系

2006. 09 ~ 2008. 07 國立交通大學 電子工程研究所碩士班