• 沒有找到結果。

Conclusion and Future Work

7.2 Future Work

There are several improvements and extensions can be considered in the future:

• Add some popular fast motion estimation algorithm

Motion estimation is the most computational part in MPEG-4 video encoder. How-ever, many fast motion estimation algorithm has been proposed, and used popularly.

We consider to add some fast motion estimation algorithm for flexibility.

• Data structure refinement

The data structure is very important to the implementation on DSPs. If we can design the more efficient data structure, the memory accesses can be significantly reduced, and the performance also can be improved.

• Dual-core loading balance

We can find the estimated frame rate in previous chapter, and the bottleneck is still the execution time of ARM part. If we can move more computation to PACDSP part, the performance will be improved by the advantage of dual-core implementa-tion.

• Demonstration on PAC system

We have done the single-core demonstration on ARM926EJ-S platform, and the major coder on DSP part have been verified on instruction set simulator (ISS) of PACDSP. Since some coding constraints are not included on the ISS, we still need to do some modification on our coding, and finally demonstrate our dual-core im-plementation on the PAC system.

• Add other MPEG-4 tools

To simplify our implementation, the error-resilience tool in MPEG-4 simple profile is neglected. However, this tool is very important when the bitstream is transmit-ted through real channels. In the future, we need to implement the techniques of error-resilience, such as resynchronization, data partition, and reversible variable length coding (RVLC). Moreover, the other advanced profiles of MPEG-4 video compression technique can be implemented to extend the capability of PACDSP.

Bibliography

[1] SoC Technology Center, Industrual Technology Research Institute, PACDSP v2.0 — Instruction Set Menu. Doc. no. PACDSP2S0000, June 2005.

[2] SoC Technology Center, Industrual Technology Research Institute, PACDSP v3.0

— Software Developer’s Bible — Vol. 1 Software Developer’s Guide. Doc. no.

PACDSP3S0001, Feb. 2006.

[3] SoC Technology Center, Industrual Technology Research Institute, PACDSP v3.0 — Software Developer’s Bible — Vol. 2 Instruction Set Manual. Doc. no.

PACDSP3S0002, May. 2006.

[4] SoC Technology Center, Industrual Technology Research Institute, PACDSP v3.0

— Software Developer’s Bible — Vol. 3 Programming Constraints and Optimized Guide. Doc. no. PACDSP3S0003, Apr. 2006.

[5] ISO/IEC 14496-2:2001, Information Technology — Coding of Audio-Visual Objects

— Part 2: Visual. July 2001.

[6] A. Puri and A. Eleftheriadis, “MPEG-4: an object-based multimedia coding stan-dard supporting mobile applications,” Mobile Networks Applic., vol. 3, pp. 5–32, 1998.

[7] A. Ebrahimi and C. Horne, “MPEG-4 natural video coding — an overview,” Signal Processing Image Commun., vol. 15, pp. 365–385, 2000.

[8] MPEG-4 Video Group, “MPEG-4 video verification model version 18.0,” doc. no.

ISO/IEC JTC1/SC29/WG11 N3908, Pisa, Jan. 2001.

[9] http://www.tnt.uni-hannover.de/project/eu/momusys.

[10] Kun-Bin Lee, Jih-Yiing Lin, and Chein-Wei Jen, “A Multisymbol Context-Based Arithmetic Coding Architecture for MPEG-4 Shape Coding,” IEEE Trans. Circuits Systems Video Technology., vol. 15, no. 2, Feb. 2005.

[11] Chung-Yen Tsai, “Software implementation of MPEG-4 video decoder on PACDSP platform,” M.S. thesis, Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, R.O.C., July 2006.

[12] J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Ap-proach, 3rd ed. San Francisco: Morgan Kaufmann Publishers, 2003.

[13] S. Sriram and C. Y. Hung, “MPEG-2 video decoding on the TMS320C6X DSP architecture,” in IEEE Signal Systems Computer Conf., vol. 2, Nov. 1998, pp. 1735–

1739.

[14] C. E. Fogg, “Survey of software and hardware VLC architectures,” in Proc. SPIE Image and Video Compression, vol. 2186, May 1994, pp. 29–37.

[15] R. Prasad and R. Korada, “Efficient implementation of MPEG-4 video encoder on RISC core,” IEEE Trans. Consumer Electronics, vol. 49, pp. 204–209, Feb. 2003.

[16] N. I. Cho and S. U. Lee, “Fast algorithm and implementations of 2-D discrete cosine transform,” IEEE Trans. Circuit Syst., vol. 38, pp. 297–305, Mar. 1991.

[17] B. G. Lee, “A new algorithm to compute the discrete cosine transform,” IEEE Trans.

Acoust. Speech Signal Processing, vol. 32, no. 6, pp. 1243–1245, Dec. 1984.

[18] C. Y. Hung and P. Landman, “A compact IDCT design for MPEG video decoding,”

in Proc. IEEE Workshop Signal Processing Systems, Nov. 1997.

[19] G. Plonka and M. Tasche, “Reversible integer DCT algorithms,” preprint, Gerhard-Mercator-Univ. Duisburg, 2002.

[20] Y. Chen and P. Hao, “Integer reversible transformation to make JPEG loseless,” in Int. Conf. Siganl Processing, Beijing, China, Sept. 2004, pp. 835–838.

[21] T.S. Chang, C.S. Kung, and C.W. Jen, “A simple processor core design for DCT/IDCT transform,” IEEE Trans. Circuits Syst. Video Technology, vol. 10, no.

3 , pp. 439–447, Apr. 2000.

[22] Texas Instuments, TMS320C64x Image/Video Processing Library — Programmers Reference, Literature no. SPRU023B, Oct. 2003.

[23] N. Ventroux, J. F. Nezan, H. Raulet, and O. Deforges, “Rapid prototyping for an optimized MPEG-4 decoder implementation over a parallel heterogenous architec-ture,” in Proc. Int. Conf. Multimedia Expo, vol. 3, July 2003, pp. 417–420.

[24] K. Ramkishor and U. Gunashree, “Real time implementation of MPEG-4 video de-coder on ARM7TDMI,” in Proc. Int. Symp. Intelligent Multimedia Video Speech Processing, May 2001, pp. 522–526.

[25] J. H. Kuo, J. L. Wu, J. Shiu, and K. L. Huang, “A low-cost media-processor based real-time MPEG-4 video decoder,” in IEEE Int. Conf. Consumer Electronics, June 2002, pp. 272–273.

[26] J. T. J. VanEijndhoven et al., ”TriMedia CPU64 architecture,” in IEEE Int. Conf.

Computer Design, 1999

自傳

江政達,男,民國七十一年十月四日出生於台北縣板橋市。高中就 讀於國立台灣師範大學附屬高級中學,民國九十四年六月畢業於交通

大學電信工程學系,並於同年九月進入交通大學電子工程研究所碩士

班就讀,於民國九十六年六月取得碩士學位,論文題目為:『MPEG-4

物件視訊編碼器在 PACDSP 平台上之軟體實現』,研究範圍與興趣為:

軟、硬體和 DSP 平台上之系統整合與開發,主要應用範圍在多媒體訊

號處理與壓縮方面。

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