Future work

The throughput of a parallel turbo decoder is dominated by the parallelism, frequency, operating efficiency, and iteration number. There are still many design challenges with respect to these factors. In the parallel architecture, the component circuits are dupli-cated to process multiple data every cycle. The maximal parallelism might be restricted due to the available area. If we could use shorter data width for all quantized symbols without performance loss, higher parallelism is possible, and the critical path delay can be decreased. For operating efficiency, the schedule with overlapping half-iterations is preferred due to less overhead. As this method can support other interleavers than QPP interleaver, it can be exploited in more applications. In order to maintain the error-correcting capability, it always takes 8 or more iterations for large blocks. Using early stopping criterion can lower the average iteration. We would like to further shorten the maximal iteration even though the transmitted data suffer from large noise. As a conse-quence, more significant speedup will be feasible by optimizing the four factors.

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