B. PCB Layout
4.1.2 Measurement
The measurement setting is shown in Figure 4.5. The measured results for DC analysis, S-parameter, Power gain, IIP3, and NF are discussed.
Figure 4.5 Measurement setting A. DC
Post-sim : square Measurement : circle
Id c (A )
Vgs (V) LNA
(a)
Vgs (V)
Idc (A)
Mixer
(b)
Vgs (V)
Id c (A )
Buffer
(c)
Figure 4.6 Gate bias sweep of (a) LNA (b) Mixer (c) Output buffer
From the Figure 4.6, the measured dc currents of LNA and mixer are closed to post-simulation but the measured dc currents of output buffer is less then post-simulation due to process variation.
B. S-parameter
(a)
(b)
Figure 4.7 S11 (a) Measurement (b) Post-simulation (range: 2 GHz ~ 3GHz)
In the Figure 4.7, the measured S11’s Smith chart has different real part value compared to post-simulation.
( ( ) 1 )
Zin gm Ls jw Lg Ls
Cgs jwCgs
= × + + + (4.2)
The real part of the S11 is composed of gm, Cgs, and Ls shown in Eq. 4.2. The measured S11 can be fitted by post-simulation results with Smith chart to fine the cause of the input matching variation.
RFIN
RFOUT
Cgs Lg
Off-chip
Ls Ld
gm Cd
Figure 4.8 Simplified LNA schematic and fitted S11’s Smith chart
The measured Smith chart with LNA gate bias equal to 0.9V can be fitted in post-simulation with an additional capacitor Cd = 300fF as can be seen in Figure 4.8.
The Cd is results form parasitic capacitance of ESD pad and PCB.
C. Power Gain Measurement setting:
1. Sweep Frequency : 2.4 GHz ~ 2.7 GHz
2. DC condition : Idc_LNA = 6mA ; Idc_Mixer = 4mA ; Idc_Buffer = 18 mA 3. LO power = 3.48 dBm (fixed IF = 10 MHz)
4. RF power = -50 dBm
Figure 4.9 Spectrum analyzer with BW resolution 10kHz and average time 100
Figure 4.10 Power gain with different frequency Post-sim : square
Measurement : circle
In Figure 4.10, the gain reduction is observed compared to post-simulation.
According to above measurement results, the gain degradation is mainly affected by the variation of input matching and output buffer’s DC current.
D. IIP3
Measurement setting:
1. Sweep bias of the input gm stage in mixer: vgs_Mixer = 0.6 ~ 1.1 V, step 0.05 V 2. RFin = -41.5 dBm at 2.6 GHz
3. RFin_delta = -41.5 dBm at 2.61 GHz 4. LOin = 4.74 dBm at 2.55 GHz 5. IF out : 50 MHz and 60 MHz 6. AIM3 : 40 MHz and 70 MHz
Figure 4.11 Spectrum analyzer for two-tone test
IIP3 (dBm)
Vgs_Mixer (V)
Figure 4.12 IIP3 performance with different vgs of input gm stage
From Figure 4.11, the IIP3 increases with raising Mixer gate bias voltage (Vgs_Mixer) and this trend meet the discussion in chapter 3.1.
E. NF
Measurement setting:
(a)
(b)
Figure 4.13 (a) NF analyzer (b) Measured result (LSB) with different IF
Because of the gain degradation, the measured NF performance is also higher than post-simulation result. (about 5.6 dB with LSB mode)
4.1.3 Summary
Table 4.1 Comparison table
*DCR : direct conversion
A figure of merit (FOM) which normalizes dynamic range to power dissipation is employed to compare the performance of the front-end circuits.
3( )
10 log
( 1)
dB
IIP mW Gain
FOM NF power
×
= − × (4.3)
Table 4.1 summarizes the measurement and post-simulation results. Because of the gain degradation, the FOM is obviously different value between post-simulation and measurement.
4.2 Interference Aware Scheme
In this chapter, these circuits of the IAS are implemented with UMC CMOS 0.18um technology. Measurement results are also shown here.
4.2.1 Layout Consideration
The circuits of the IAS deal with the analog signal (frequency is lower than 100 MHz), so the characteristic impedance is less important than RF signal line. For analog signal, the device layout symmetry is the main consideration.
A. Chip Layout
In Fig 4.14, the layout of two IASs for I and Q path include the LPFs are illustrated.
Figure 4.14 Layout view of the IAS with two paths (I and Q)
1. Vp and Vn: the input of LPF 2. Outp and Outn : the output of LPF
3. C1 (a/b) and C2 (a/b) : the two paths’ output of peak detectors 4. Digit : digital output
5. Vcom : the reference voltage of CMFB
Figure 4.15 The photograph of the IAS B. PCB Layout
Figure 4.16 The PCB layout of IAS with two paths
4.2.2 Measurement
In Figure 4.17, the IAS measurement setting uses ESG to generate the carrier signal and interference. The instrument setup is employed to the output DC voltages of peak detector, LPFs, and digital.
Figure 4.17 The IAS measurement setting A. DC
The dc voltage is measured with no input signal stimulating.
1. Post-simulation Idc_IAS (I-Q path) = 5.267 mA (include two LPFs) Measurement Idc_IAS (I-Q path) ~ 8 mA
2. The output dc voltages of peak detectors:
Post-simulation:
VC1 and VC2 = 0.385 mV Measurement:
VC1 ~ 0.35 mV ; VC2 ~ 0.85 mV 3. The output DC voltages of LPF:
Post-simulation:
Voutp = Voutn = 0.9 V Measurement:
Voutp ~ 1.12 V ; Voutn ~ 1.43V
5. Vcom could be changed to adjust the peak voltage (VS and VI) in circuit design but it doesn’t work in this implementation.
According to above measured results, the IAS suffers from mismatch due to process variation.
B. Two-Tone Test
Two ESG instruments are used to generate the carrier signal and interference signal.
Measurement setting:
1. Sweep the interference power : -30 dBm to 15 dBm (fixed frequency 20MHz) 2. fixed carrier signal power : -30 dBm (fixed frequency 5 MHz)
Post-simulation: when interference power > -21 dBm, the digital out is equal to VDD.
Measurement: the digital out is always equal to VDD in the sweep range.
The implemented IAS doesn’t work correctly because of the variation of DC bias points.
Chapter 5 Conclusions
5.1 Summary
An interference aware scheme composed of four building blocks including signal distinction, envelope detection, error correction and mode selection is proposed and designed.
A CMOS RF receiver front-end with dual linearity modes including LNA and mixer for WiMAX standard is implemented in a 0.18um CMOS tech. At high linearity mode it has IIP3 of -9.8 dBm and consumes 32.4mW; at low linearity mode it has IIP3 of -12.9 dBm and consumes 19.8 mW. The power gain is about 14 dB and NF is about 11 dB for dual modes.
By combining with the proposed interference aware scheme and dual-mode RF receiver front-end, the operation mode of the receiver front-end can be automatically selected according to the interference condition by the low-power IAS and 5.5dB improvement of system interference tolerance is achieved from co-simulation results.
5.2 Future Works
5.2.1 Fully Integrated Chip
In this thesis, the IAS and RF front-end are implemented separately. But fully integration of RF receiver front-end and IAS has the cost benefit for realistic implementation. The DC offset must be taken into consideration for combining these two blocks because it can corrupt the signal and, more importantly, saturate the following stages, such as IAS and LPF. DC offset cancellation (DCOC) technique [17]
can be employed to compensate the DC offset due to direct conversion architecture.
Figure 5.1 DC offset cancel block
In Figure 5.1, the DC offset cancel block consists of passive LPF, a transconductance amplifier, and a current amplifier.
Figure 5.2. DC offset cancel circuit (DCOC)
The operation of this DCOC circuit in Figure 5.2 is as follows. First, DC offset voltage detected by passive LPF is amplified and is converted to the differential currents (I11, I12, I21, and I22) by the transconductance amplifier. Then, these differential currents flow into the single-ended differential current amplifiers where
the differential components are amplified and the common currents are subtracted with perfect matching of the input pairs. Therefore, only DC offset component is extracted and is used for DC offset correction.
5.2.2 Dynamic Range of the IAS
The sensitivity of the designed IAS in this thesis focus on carrier signal that is equal to -67.5 dBm witch is the sensitivity of 64QAM-3/4 modulation in WiMAX system. For the lowest order modulation such as BPSK-1/2, the designed IAS cannot detect the sensitivity level (-96.7 dBm) of the BPSK-1/2 due to the two amplifiers (Amp_S and Amp_I) in signal distinction. For the lowest sensitivity level (BPSK-1/2), these two amplifiers need higher gain to make IAS work correctly. On the contrary, for the highest sensitivity level (64QAM-3/4), lower gain amplifiers are need. Here, we propose a modify IAS to overcome this issue.
Figure 5.3 Modified IAS
In Figure 5.3, the modified IAS has a block called “Gain Switch”. When carrier signal isn’t detected by IAS, the gain switch can change the gain of Amp_S and Amp_I to high gain mode. On the contrary, when carrier signal is higher enough, the gain switch can change the gain of Amp_S and Amp_I to low gain mode. Using the gain switch can increase the dynamic range of the IAS.
VS_maximum (Amp_S is at saturation) > VREF > Vswitch
(These values are closed to each others.) VL > VS_minimum (No input signal) (VL is slightly more than VS_minimum)
1. Highest sensitivity mode è Lowest sensitivity mode
At initial condition, the IAS is in low gain mode. When carrier path peak level is less than VL, the IAS can be changed to high gain mode by gain switch and detects the lowest sensitivity signal.
2. Lowest sensitivity mode è Highest sensitivity mode
At initial condition, the IAS is in high gain mode. When carrier path peak level is more than Vswitch, the IAS can be changed to low gain mode.
For advanced discussion, the lower sensitivity of some type modulation signal such as BPSK-1/2 (-96.7 dBm), the VOS of the modified IAS should lower than 89 uV at the lowest sensitivity mode.
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Vita
for WiMAX Applications具干擾偵測功能之 WiMAX 射頻前端接收器設計 論文發表：
Chia-Hsin Lin, Wen-ShenWuen, Kuei-Ann Wen, “An Interference Aware RF Receiver Front-End Design for WiMAX Application” EuMW 2008.