Chapter 1 Introduction
1.3 Main Results and Thesis Organization
1.3.1 Main Results
A low power 10-bit 500-kS/s SAR ADC for implantable epilepsy devices is designed and measured. In order to achieve low power design, the power
consumption of the capacitor array must be first considered. An new capacitor array is proposed to significantly reduce power consumption. First, a binary weighted capacitor array is cascoded to reduce 50% switching energy. A binary weighted capacitor array has good capacitance mismatch performance, but consumes a lot of power dissipation. Two same capacitors are cascoded to reduce total capacitance and power consumption. A cascoded binary weighted capacitor array also has better capacitance mismatch performance when using the same size of the unit
capacitance. Then, part of the junction-split switching method is applied to further reduce power dissipation. The junction-split switching method is very efficient, but has problems of floating elements and capacitance mismatch. Part of this switching method is applied to take the benefit and avoid those problems
The proposed SAR ADC is simulated with low power consumption of 80 µW, SNDR of 59.26 dB, ENOB of 9.55. This design is implemented in TSMC 0.18-µm CMOS process.Measurement results of the fabricated SAR ADC perform low power consumption of 85 µW, SNDR of 44.10 dB, and ENOB of 7.03. The chip area is 1 mm2. Modified simulation results perform low power consumption of 83 µW, SNDR of 57.53 dB, and ENOB of 9.26.
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1.3.2 Thesis Organization
This thesis is divided into four chapters. Chapter 1 introduces the background and the motivation of this research. The proposed SAR converter will be presented in Chapter 2. Design consideration of the converter is discussed in Section 2.1.
Then the design procedure is presented in Section 2.2. Post-simulation results are shown in Section 2.3. The experimental results will be shown in Chapter 3. Finally, the conclusions and future work will be presented in Chapter 4.
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Chapter 2
Circuit Design and Simulation Results
2.1 Design Consideration
The successive approximation (SAR) analog-to-digital converter (ADC) has recently been widely used for moderate-speed moderate-resolution applications where the power consumption is of major concern. The major advantage of SAR ADC is simple and low power because the SAR ADC does not need operational amplifiers.
Two major design issues, which decide the performance of SAR ADCs, should be thought over to achieve a good and robust design. First, a suitable unit
capacitance size for the capacitor array is chosen to reduce the thermal noise and capacitance mismatch. The accuracy of SAR ADCs is significantly influenced by these two factors. However, when SAR ADCs are used for high resolution applications, the unit capacitance size is determined by capacitor mismatch. The thermal noise is small enough to neglect.
The other major design issue is the efficiency of switching methods for the capacitor array. For high-resolution applications, the switching energy dominates the total power consumption of the SAR ADC. Many efficient switching methods are developed to reduce the switching energy. The switching energy is significantly decreased by those methods.
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2.2 Circuit Design
2.2.1 A Conventional SAR ADC
A conventional binary weighted SAR converter is shown in Fig 12. A SAR converter is basically composed of three main parts. They are a capacitive digital-to-analog converter (DAC), a successive approximation register, and a comparator. A capacitive DAC and a successive approximation register produce an approximation of the input signal. A comparator is composed of preamps and a latch, and determines whether the approximation is too high or too low. The approximation is improved by knowing the result of the last comparison, and the process is repeated until the entire digital word is decoded. The algorithm is described below.
Figure 12 A conventional SAR ADC
In the sampling cycle, SSAMPLE is high, and the entire capacitor array stores the voltage VMID - VIN. At the end of sampling cycle, SSAMPLE is reset to low. Then, the successive conversion cycles are coming. At the beginning of conversion, the MSB cap Cb is connected to VREF, causing VX to settle to
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= − +
( 1)
And the latch output is
= 1, >
The latch output controls the next switch transition. If D1 is high, the second largest capacitor is connected to VREF (SH, b-1 =1), raising the voltage at VX (this action is called an “up” transition). On the other hand, if D1 is low, Cb is returned to ground and Cb-1 is connected to VREF (a “down” transition).
The above process is repeated for successive capacitors in the array. At each stage, the value of VX is
= !" − + #$
#$+ #% ( 3)
Where CT is the sum of all capacitors connected to the reference voltage (VREF), and CB is the sum of all capacitors connected to ground:
#& = ' ()*#+ ,-. ( /012 3243 56,(= *
2.2.2 The Proposed SAR ADC
Figure 13 shows the architecture of the proposed SAR ADC. A new DAC is proposed to significantly reduce power consumption, and a better switching method [7] is applied to the DAC, too.
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Figure 13 The proposed SAR ADC
The following sections will detailed describe the design of each block, including the DAC, the comparator, and the successive approximation register.
2.2.3 Digital-to-analog converter
The DAC is the most critical component of SAR ADCs, and should be considered carefully. First, the total area is dominated by the DAC composed of many
capacitors. Then, although there is no static power consumption from the capacitor array during the operation, the transient power becomes more enormous because of requiring the higher accuracy and speed performance. The DAC consumes a major portion of the total power. Therefore, how to reduce the area and the power
consumption of the DAC is the most popular research issue about SAR ADCs in recent years.
The unit capacitance size and the binary weighted capacitor ratio are the reasons that a conventional capacitor array occupies so much area. The thermal noise and the random mismatch between two adjacent capacitors resulting from
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different technology decide the unit capacitance size. In most conditions, the effect caused by the thermal noise is too small compared with the last significant bit (LSB) voltage of ADCs so that it could be ignored. Without the effect of the thermal noise, the random mismatch between two adjacent capacitors is the only factor, which decides the unit capacitance size. In a few words, the higher accuracy the ADC requires, the larger size of the unit capacitance is.
A binary weighted capacitor array is the easiest way to implement a DAC, but it requires many different values of capacitors, which demands much area. For an N-bit capacitor array, the largest capacitor is 2N-1 times larger than the unit capacitor.
Although many non-binary weighted capacitor arrays are developed to reduce area and power consumption, they also make the accuracy performance worse. In short, this is an area / accuracy tradeoff. The most efficient way to reduce area is to implement a DAC by using the most advanced technology. The random mismatch between two adjacent capacitors could be improved by the newest technology.
The other design issue of a DAC is the power consumption. For a binary
weighted capacitor array, the power consumption of an N+1 bit resolution capacitor array is 2 times more than an N bit resolution capacitor array. Therefore, for
high-resolution applications, the power consumption of a DAC becomes enormous.
However, a conventional switching method is very inefficient because many unnecessary switching steps waste considerable power. The operations of the “up”
transition and the “down” transition are described in Fig 14. During the operation of the “up” transition, the value of VX is lifted from 1/2 VREF to 3/4 VREF, and no power is wasted. However, during the operation of the “down” transition, the value of VX is first down to zero, and then lifted to 1/4 VREF. Obviously, there is much power wasted during the operation of the “down” transition because the
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unnecessary charge / discharge actions. How to reuse the charge saved in the capacitor array is an efficient way to improve the switching method.
Figure 14 (a) the “up” transition (b) the “down” transition
A. A cascaded capacitor array
A binary-weighted capacitor array is chosen because of the capacitance
mismatch performance, which decides the accuracy of the SAR converter. Instead of a conventional binary weighted capacitor array, a cascoded binary weighted capacitor array is used to have the same capacitance mismatch performance and consume less power dissipation. A cascaded capacitor array is shown in Figure 15.
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Figure 16 (a) a conventional capacitor array (b) a cascoded capacitor array
When catching sight of this architecture for the first time, the first impression is that a cascoded array occupies more area. However, the unit capacitance size of a cascoded capacitor array is different from a conventional binary weighted capacitor array.
In this design, the total capacitance is large enough to neglect the effect of the thermal noise. Therefore, the unit capacitance size is decided by the random
mismatch between the two adjacent capacitors. The mismatch factor is given by the TSMC 0.18µm technology. The detailed Monte-Carlo analysis is performed to determine the value of the unit capacitance. Results of the analysis are shown in Table II. From the results of the analysis, a smaller size of the unit capacitance for a cascoded capacitor array is needed to meet the same accuracy requirement.
Ideally, the size of the unit capacitance for a cascoded array is half of the value for a conventional array. That is to say, no more area is required to apply this
architecture. Because of the limitation of the technology, the size of the unit capacitance is chosen as 20 fF.
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Cunit
(µm×µm)
Mismatch (LSB)
Conventional Capacitor Array Cascoded Capacitor Array
4×4 0.46 0.33
Table II The Monte-Carlo analysis of the random mismatch
A cascoded capacitor array only consumes half power consumption of a conventional capacitor array when using the same size of the unit capacitance.
B. Junction-Split switching method
In addition to applying a cascoded capacitor array, the method of the
junction-split capacitor array is applied to the proposed capacitor array in order to further decrease power consumption. The switching transition of the junction-split capacitor array is shown in Figure 17. In case of output code 000, the J-S capacitor array consumes one seventh of the energy required in the conventional capacitor array. The switching energy consumed by a conventional capacitor array at each step is computed as follows, where E0, E1 and E2 represent the energy required to determine D0,D1, and D2.
9+= − :#(−*
− +) = # ( 6)
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On the other hand, the switching energy consumed by the J-S capacitor array at each step is computed as follows:
9+ = − #(−*
Figure 18 Switch transitions of the 3-bit capacitor array in case of code 000.
(a) For the conventional capacitor array. (b) For the J-S capacitor array
The power consumption is remarkably reduced by the J-S capacitor array, but the accuracy performance is also significantly worse by the J-S capacitor array. For the purpose of avoiding the accuracy problem, the switching method is only used to reduce the power consumption of the MSB decision.
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C. The proposed capacitor array
The schematic of the proposed DAC capacitor array is shown in Figure 19.
Figure 20 The schematic of the proposed capacitor array
The operations of the proposed capacitor array are as follows. First, for the purpose of avoiding charge accumulation between two series capacitors, the charges on the two capacitors are released by turning on SRET, SSAM2, and SSAM3. Otherwise, SSAM1 and SSAM4 are off. After all charges on the capacitors are released, SRET is off, but SSAM2 and SSAM3 are still on. At the same time, the operation of sampling is started by turning on SSAM1. At the end of the sampling cycle, SSAM1 is off to end the operation of sampling. Besides, SSAM2 is also off. After the operation of sampling is completed, the conversion is started. The bottom of C9B is first connected to VREF, and others are connected to the ground excluding the bottom of C10B. The bottom of C10B remains floating. The value of VX is as follow.
= − +*
( 12)
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If VX is higher than VMID, the most significant bit (MSB) D10 is 0; alternatively, D10
is 1. After the first conversion cycle, SSAM4 is on for the operation of the J-S
switching method. No matter D10 is 1 or 0, SH,9 keeps on during the second cycle of the conversion. However, if D10 is 0, the bottom of C10B is connected to the ground.
The value of VX is as follow.
Again, the value of VX is compared with VMID to decide the second significant bit D9. According to the value of D9, the bottom of C9B is connected to the ground if D9
is 0; otherwise, the bottom of C9B is connected to VREF.
The remaining bits are going to be converted as follows. When the conversion cycle for Di is coming, the bottom of CiB is first connected to VREF. Then, the connection of CiB depends on the result of Di as follows.
( = G*, H2I J-33-K -, #(8 7/ 1-LLI13IM 3-
+, H2I J-33-K -, #(8 7/ 1-LLI13IM 3- 32I N.-0LM ( 15) There are ten conversion cycles needed for 10-bit resolution. When the
conversion is completed, 10 bit output codes are transmitted at the same time. All control signal status are listed inTable III. The switching comparison is shown in Figure 21. The proposed capacitor array consumes only 40% power dissipation of a conventional binary weighted capacitor array. Figure 22 shows the timing diagram for the conversion. A complete signal conversion takes twenty clock cycles to finish.
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Figure 23 Switching energy comparison
Operation
Switch Status
ON OFF
Reset SRET, SSAM2, SSAM3 SSAM1 , SSAM4
Sampling SSAM1, SSAM2, SSAM3 SRET, SSAM4
Conversion of D10 SSAM3 SRET, SSAM1, SSAM2, SSAM4
Conversion of D9~D1 SSAM4 SRET, SSAM1, SSAM2, SSAM3
Table III Signal Control
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Figure 24 The timing diagram
In order to finish a good design for the proposed capacitor array, the common centroid capacitor array layout is required. Figure 25 shows the detailed floor plan for the proposed capacitor array.
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Figure 26 Floor plan of common centroid capacitor array
2.2.4 Comparator
For low-resolution applications, the comparator consumes more power than the DAC. Recently, the SAR architecture is applied to high-resolution applications, and the DAC dominates the power consumption of the ADC. In addition to low-power design of the comparator, the offset voltage of the comparator attracts more
attention for high-resolution applications. The block diagram of the comparator is shown in Figure 27. Three stages of preamps are used to significantly reduce the offset voltage. The latch is used to yield the output rapidly. The detailed circuits of
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the comparator and the latch are shown in Figure 28. Table IV and Table V shows transistor sizes of the preamp and the latch.
Figure 29 The block diagram of the comparator
Comp+ Comp-
Comp-Figure 30 (a) The circuit of the preamp (b) The circuit of the latch
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Transistor W/L (μm) Multiple
M1, M2 0.5/0.18 4
M3, M4 0.25/6 1
Mb1 20/0.18 4
Table IV Transistor sizes of the preamp
Transistor W/L (μm) Multiple
Table V Transistor sizes of the latch
2.2.5 Successive Approximation Register
Digital control circuits include the successive approximation register and control logics. The successive approximation register generates the pulse signal for every bit conversion cycle, and stores the outputs generated by the comparator. The control logics are composed of many simple logic gates, and control the switches to connect to the ground or VREF.
The successive approximation register, which is composed of many D Flip-Flops, is shown in Figure 31. The detailed circuit of a D Flip-Flop is shown in Figure 32.
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Figure 33 The two main parts of the successive approximation register. (a) The pulse generator generates the pulses needed for every bit-cycle operation. (b) The register stores the output code during the coversion.
Figure 34 The detailed circuit of a D Flip-Flop.
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2.3 Post-Simulation Results
2.3.1 Dynamic Performance
In addition to the DNL and INL, which are usually referred to as static (low frequency) performance measures, another metric to determine the dynamic performance of the ADC is to measure the distortion ratio by applying a sinusoidal input signal and analyze the output codes in terms of frequency content. The frequency power spectrum can later be used to calculate the signal-to-noise and distortion ratio, SNDR, which is the power strength and the
effective-number-of-bits, ENOB, which is the actual resolution of the ADC. The ENOB is defined as:
9OPQ =5OR − *. AT
T. + ( 16)
where the SNDR is the signal power divided by any distortion and noise in the ADC output with unit in dB.
Figure 35 shows simulation results of 50 kHz 1.8V input sine wave. From the FFT analysis, the signal to noise and distortion ratio (SNDR) is calculated as 59.26 dB, and the effective number of bits (ENOB) is 9.55. In Figure 36, detailed simulation results are performed to compare SNDR at different input frequencies and different corners. Table VI is shown the detailed data number.
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Figure 37 FFT Analysis of TT corner with 1.8V 5.6 kHz input sine wave
Figure 38 SNDR of different input frequencies and different corners
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Corner Input frequency SNDR
TT
Table VI SNDR of different input frequencies and different corners
2.3.2 Static Performance
The DNL error defines the difference of the input width of each code with the ideal input width. Although each unique ADC output code corresponds to a certain input signal range, the output code width can be slightly different in reality. When the output code corresponds to a large range of the input signal, it means the code appears too many times comparing with other codes. This results the DNL error to be positive. Consequently, a narrow output code indicates a negative DNL. The DNL equation is defined as:
OU(4) =V(4) − V7MI4W
V7MI4W ( 17)
The DNL error unit is defined as an ADC LSB. If the DNL error is -1LSB, it means
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there is a completely missing output code. As mentioned earlier, the output offset and gain error must be removed before calculating the DNL and INL.
The INL defines the error between the appearance of a certain output code and the actual ideal appearance of the output code. This is also the integral of the DNL errors. INL error is also presented in terms of ADC LSB. Because the INL
measures the integral of the output code errors, the magnitude of an INL error can be greater than 1LSB without having any missing output codes. Figure 39 shows the differential nonlinearity (DNL) of the proposed SAR ADC. The simulation result of the DNL is +053/ -0.64 LSB. The integral nonlinearity (INL) is shown in Figure 40, and the value is +0.66/ -0.58 LSB.
Figure 41 DNL
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Figure 42 INL
2.3.3 Simulation Results and Comparison
The specification table of the proposed SAR ADC is shown in Table VII. In Table VIII, the comparison table shows the comparison with other references.
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Target Specifications
Post-simulation
Technology TSMC 0.18-um CMOS Process
Resolution 10
Sampling Rate(S/s) 500 K
Input Range 0~1.8 V
Differential Nonlinearity
<0.5 0.63/-0.54
Integral Nonlinearity <1 0.66/-0.58
SNDR@DC >55.94 59.26 dB
ENOB@DC >9 9.55
SNDR@Nyquist Rate >55.94 58.89 dB
ENOB@Nyquist Rate >9 9.49
Power Consumption 80 µW
Figure of Merit (fJ/Step)
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Table VII Simulation results
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Table VIII Comparison Table
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Chapter 3
Experimental Results
3.1 Layout Descriptions
The die microphotograph is shown in Figure 43. In Figure 44, the location of each individual circuit block is marked on the complete SAR ADC layout. The overall circuit area is 1 mm2. From this figure, it can be seen that the majority of the ADC area is occupied by the capacitor array. The entire layout was done very conservatively in terms of area, especially the capacitor array. The sensitive comparator circuit is separated from the successive approximation register circuit by large space. In this way, the coupling effect could be suppressed.
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Figure 45 Die microphotograph
3.2 Measurement Setup
The measure environment setup is shown in Figure 46. The signal generator SRS DS360 is used to generate hundreds of kilo hertz sine wave. The supply voltage is from Agilent E3631A , which provides a stable 1.8 V for the proposed ADC.
Finally, The logic analyzer Agilent 16822A is used to receive 10-bit output code of the ADC.
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Figure 47 Measurement Setup
3.3 Measurement Results
This section describes the performance of the ADC which is packaged and tested
This section describes the performance of the ADC which is packaged and tested