As semiconductor manufacturing technology advances, integrated circuit industry had used laser light source of shorter wavelength (193 nm) together with chemically amplified photoresist (CAPR) in order to improve resolution for enabling device scaling in accordance to Moore’s Law. However, the energy of laser light source originated from deep ultraviolet (DUV) ray is much lower in the range around 10-30 mJ/cm2, which is ~1/10 times of I-line light sources of traditional ultraviolet ray with mercury light source energy about 300-500 mJ/cm2 as listed in Table 1.1 [1]. In order to compensate such low energy, scientists had implemented an additional post exposure bake (PEB) immediately after the exposure of DUV resist in which PAG generates proton upon radiation. Protons H+ created by PAG upon exposure can subsequently catalyze polymer’s acid labile protecting group (ALPG) and de-protecting chemical reaction during PEB step (~120-140 ℃) with other new by created proton H+ again. The proton H+ will continue and catalyze other ALPG de-protecting reaction. Through such chain reaction, the number of times of de-protecting reaction will expand by several hundred folds [2].
As a result, poor temperature control during PEB step and H+ dissolution rate may have adverse effect on the resist patterning as illustrated by the examples of critical dimension (Table 1.2) and line edge roughness (LER)[3-4]. When the gate width/length is concerned, the variation of CD will influence the threshold voltage, Vth, leakage current, and Ioff characteristics [5-7]. More over the dissolution rate and H+ have been reported to affect LER significantly as illustrated in Figure 1.1 [8].
According to the International Technology Roadmap for Semiconductor (ITRS), there is a great demand of solutions and control for CD and line edge roughness (LER)
(Table 1.3) [9].
So far, the industry has addressed this problem by implementing a CD measurement step and reworking the lithography step for CD unlisted in the specifications. When DUV technology is introduced, numbers of measuring instruments and sampling frequency have been increased to send out-of-specifications wafers bake to rework and patterning step incurring increased equipment cost, production queue time. Recently, resist profile measurement based on scatterometry [10] has been adopted to provide accurate feedback and readjust the process parameters under exposure and PEB.
In this thesis, we will focus on the investigation of the hardware temperature control in PEB steps and its correlation between ΔT parameter and CD. The objective is to use a simple ΔT parameter to reduce rework rate and yield loss without incurring too much cost.
In order to examine the correlation between ΔT and CD variation, a high resolution SEM is used to examine CD with resolution of 1 Å which is capable of observing any CD variation induced by heat and the changing behavior of photoresist material CD.
To be specific, we use three types of photoresist, namely, I-line photoresist, DUV 248 nm photoresist, and DUV 193 nm photoresist using two kinds of bakes, PB and PEB.
Spacers of six different thicknesses (2.5 mm, 2.0 mm, 1.5 mm, 1.0 mm, 0.5 mm, and 0 mm) are used to place and hinder the wafer from placing higher than the plate.
According to the measurement result influences of CD variation are found when PB is greater than PEB. Because the insufficient harden PR, photo-acid generator (PAG) in room temperature will be constant during the period of diffusion and micro flow, and in the subsequence PEB heat energy driven PAG move more violet. H+ micro flow of the exposure area is actually non-directional due to the result of un-hardening which has led to the mass out warding of proton diffusion of CD
making. When it is insufficient to bake with PEB, the opposite direction of influence will cause diminish in the CD.
In addition, a three-dimensional finite-element model using commercial software, ANSYSTM was employed to examine the wafer surface temperature of various hardware and contact gap conditions. Such as particle contamination, wafer tilt, and ring type backside contamination. This model can be employed to simulate narrow gap case, when the spacer thickness smaller than 400 µm. In the real apparatus is too difficult to put on the plate and take out of plate, in such thin spacer is likely to be crocked and make the experiment data unstable. In addition, model is used to predict 100 µm particle at backside center of wafer surface temperature drop from 120 ℃ to 110.6 ℃ and via CD shift 11.5 nm. Also, it is use to simulate the case of a ring pattern pollution on wafer backside, because there is no good method to do a ring pattern coating at wafer backside for experiment. Modeling resume predict for 100 µm pollution on wafer backside at backside center of wafer surface temperature drop from 120 ℃ to 106.4 ℃ and the via CD shift 16.7 nm.
This thesis is organized into five chapters, which are briefly described below:
Chapter 1 introduction
Chapter 2 describes the literature review of key photoresist technologies and the motivations of this study.
Chapter 3 illustrates the theorems of interferometry and finite element analysis, and describes the procedures of sample preparation.
Chapter 4 covers experimental, results and discussion.
Chapter 5 summarizes key findings and contributions of this thesis.
Table 1.1 Selected excimer laser for lithography [11-13].
Table 1.2 Effect of PEB bake temperature on CDs [14-15]
PR Type of PR Supplier Sensitivity (nm/℃)
APEXE 248 nm DUV Shipley 16.0
UV2HS 157 nm DUV Shipley 7.5
Version 1B 193 nm DUV IBM 3.8
UV6 248 nm DUV Shipley 2.6
TM-461 248 nm DUV JSR 2.6
DP-024 248 nm DUV TOK 1.8
ARCH 2 248 nm DUV Arch 0
R2J 248 nm DUV JSR 0
Table 1.3 Critical dimension memory technology based on ITRS 2007 Year of production 2008 2009 2010 2011 2012 2013 2014 2015 2016
DRAM pitch (nm) 57 50 45 40 36 32 28 25 23
Flash pitch (nm) 45 40 36 32 28 25 23 20 18 DRAM/Flash CD
control (3 sigma nm) 4.7 4.2 3.7 3.3 2.9 2.6 2.3 2.1 1.9 Gate CD control
(3 sigma nm) 2.3 2.1 1.9 1.7 1.5 1.3 1.2 1 0.9 Absorber LER
(3 sigma nm) 3.2 2.8 2.5 2.2 2 1.8 1.6 1.4 1.3
Figure 1.1 Schematic diagrams and, definitions of line edge roughness (LER) and line width roughness (LWR)