In this chapter, we first introduce the importance low power design, and, then, discuss
the sources of power consumption on bus and the effects of crosstalk-toggling transitions. The
research motivation and objective are then introduced. The organization of this thesis is
elaborated in the end.
1.1 Importance of Low Power Design
As the complexity of system-on-chip (SoC) design increases, power consumption is
becoming one of the most important design issues especially for embedded systems due to
heat reduction, cooling cost reduction, longer cell life, and etc. In addition to these problems,
energy efficiency has become an important characteristic of product quality. In mobile devices
such as cellular phone and other handheld devices, energy efficiency further determines the
usability and acceptance of these products. Since these products are battery-powered and the
required usage amounts are increasing rapidly, low power design for these systems becomes a
very important research topic.
1.2 Sources of Power Consumptions on Buses
The power consumption of bit transitions on bus lines is one of the major sources to the
total power consumption. The power consumption by bit transitions on bus lines comes from
charging and discharging the capacitance for data transmission. The bit transitions can be
classified into self-transition and coupling-transition of capacitances [1]. As CMOS processes
scale down to the deep submicron level, both self-capacitance and coupling-capacitance needs
to be taken into account. Capacitance between a bus line and ground is called self-capacitance
(Cs), and capacitance between adjacent bus lines is called coupling-capacitance (Cc). Both
capacitances are shown in Figure 1-1.
Cs Cs Cs Cc
Cc
Cs=Self-capacitance Cc=Coupling-capacitance Bus lines
Figure 1-1：Self and coupling-capacitance for buses
Self-transitions are bit transitions on each individual bus line which make
self-capacitance charging and discharging. Coupling-transitions are bit transitions between
adjacent bus lines that cause a voltage level difference and thus cause coupling-capacitance
charging and discharging. Coupling-transitions can be subdivided into two types, crosstalk
1-bit transitions and crosstalk-toggling transitions. Moreover, crosstalk 1-bit transitions occur
in the cases when only one of the bus lines switches between adjacent bus lines, for examples
{00 01}, {00 10}, {11 01}, {11 10}. Crosstalk-toggling transitions occur when
both of the adjacent bus lines switch to the opposite directions, for examples {01 10}. And
the remaining cases, for examples {00 00}, {11 11}, {00 11}, do not trigger any
activity on coupling-capacitance. Figure 1-2 shows the examples of a crosstalk 1-bit transition
and a crosstalk-toggling transition.
0→0
0→1
Crosstalk 1-bit-transitions {00 → 01}
0→1 1→0
Crosstalk-toggling transitions {01 → 10}
Figure 1-2：Examples of a crosstalk 1-bit transition and a crosstalk-toggling transition
1.3 Effects of Crosstalk-Toggling transitions
With process technology moving toward the deep submicron level, coupling-capacitance
between adjacent bus lines is becoming ever more prominent. The ratio of
coupling-capacitance to self-capacitance increases as process shrinks [2]. Crosstalk-toggling
transitions cause not only more power consumption but also longer data transmission delays.
The data transmission delay from crosstalk-toggling transition is at least twice of that of other
transitions [3]. As regards power consumption, the power consumption due to
crosstalk-toggling transitions is at least four times of that of other transitions [1]. Thus, the
effects of crosstalk-toggling transitions are much more serious than that of other transitions.
1.4 Research Motivation
Since the effects of crosstalk-toggling transitions are much more serious than that of
others, many bus-encoding schemes have been proposed to totally avoid the
crosstalk-toggling transitions. The purpose of crosstalk-toggling-free bus encoding schemes is
to reduce data transmission delay in synchronous circuit designs. However, opportunities still
exist in previous crosstalk-toggling-free bus encoding schemes to reduce total power
consumption on buses at the same time with crosstalk-toggling free.
The power consumption on instruction bus constitutes great portion of total power
consumption on buses since a processor typically accesses instructions every instruction cycle
and the bit patterns of instruction bus is less regular than that of its address bus. However,
instructions are compiled at static time. There are opportunities to deal with instructions in a
post-compilation phase. For example, a typical ISA exhibits regularity that the register fields
are in fixed positions within the instruction encoding, and the register fields constitute a
significant part of an instruction word. Choosing registers appropriately may reduce the power
consumption of instruction bus [4]. Therefore, it is possible to reduce the power consumption
by generating instructions which consume less power.
1.5 Research Objective and Approaches
In this thesis, instructions are handled at static time to further reduce power consumption
for a crosstalk-toggling-free-coded instruction bus with no extra hardware and performance
loss. This goal is achieved by exploiting the characteristics of code-words on
crosstalk-toggling-free encoded bus. We figure out the power consumptions on
crosstalk-toggling-free encoded instruction bus that depend only on the number of 1s of
code-words. Thus, the instructions which have less 1s after crosstalk-toggling-free bus
encoding are generated. Moreover, register relabeling is used for relabel registers of
instructions, and our modified register relabeling method can consider only the register
number itself. Furthermore, the relabeling scope may be a smaller one that provides more
opportunities to reuse register numbers with less 1s after crosstalk-toggling-free bus encoding
resulting in fewer transitions. Consequently, our approaches will be suitable for
crosstalk-toggling-free-coded instruction bus so as to reduce the bit transitions on instruction
bus for power reduction.
1.6 Organization of This Thesis
The remaining chapters of this thesis are organized as follow. Chapter 2 introduces the
source of power consumption and analytical model of delay and discusses previous related
researches on crosstalk-toggling free and power reduction techniques for instruction bus. In
Chapter 3, we illustrate our power reduction techniques for instruction bus. The experimental
environment, simulation results and relative analysis are presented in Chapter 4. Finally, we
summarize our conclusions and future works in Chapter 5.